3D Illustrations Content Over OCP.


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CPU, memory and illustrations transport frame an own solidarity associated by the north extension ... Cycle from client prerequisites to outline and confirmation is short ...
Transcripts
Slide 1

3D Graphics Content Over OCP Martti Venell Sr. Check Engineer Bitboys

Slide 2

Mobile Graphics Trends Multimedia telephone shipments with sight and sound quickening agent

Slide 3

Graphics Architectures Traditionally CPU, memory and representation transport shape an own solidarity associated by the north scaffold Graphics processor has committed Memory transmission capacity hungry

Slide 4

Block Diagram of the Bus Interface

Slide 5

Key Features: Pipeling Pipelining in the OCP Specification: "the arrival of read information and the arrangement of compose information might be postponed after the presentation of the related solicitation" Bus latencies can be remunerated by sending exceptional solicitations Compensation of the transport latencies can be accomplished with: Intelligent pre-bringing instruments Smart storing

Slide 6

Key Features: Byte Enables "Exchanges of not exactly a full expression of information are upheld by giving byte empower data that determines which octets are to be exchanged." When composing 256 piece burst to the shading cradle a few pixels are needed to stay as they were Not bolstered by all transport conventions When composing 256-piece burst of the information, all pixels may not be substantial With BE bolster full blasted can be used Without BE backing a wide range of short composes must be done

Slide 7

Key Features: Threading Supports simultaneousness and out-of-request handling of exchanges Multiple wellsprings of memory gets to Gives an open door for various velocity memory gets Simplifies the outline, since return information can be related to the ID

Slide 8

The SoC System From a 3D Graphics Point of View Three viewpoints: memory transfer speed, framework transport and the illustrations processor Memory transmission capacity sets the execution furthest utmost for memory concentrated scenes (e.g. mixing). Dormancy remuneration drives the arrangement of the illustrations center inside the points of confinement permitted by the framework transport . Computational escalated (e.g. confounded shading) scenes are constrained to the illustrations processor\'s pipeline proficiency and clock recurrence.

Slide 9

System\'s Bus Architecture 1/2 Limitations: most extreme burst size and the accessibility of pipelining solicitations Since the principle memory gets to are focused to the outer DRAM it bodes well to make long blast gets to over the framework transport Various keen storing plans are connected to ensure that none of the framework transfer speed goes to squander The accessibility of byte empowers in the illustrations processor\'s transport interface boosts the burst size subsequent to there is no compelling reason to part potential long blasts into littler ones

Slide 10

System\'s Bus Architecture 2/2 The second issue is the memory inactivity of the framework which incorporates the aggregate dormancy from the design processor to the outside memory and back One effective approach to make up for this idleness is to send different remarkable solicitations to the transport interface By pipelining the solicitations along these lines a consistent information stream can be encouraged to the memory transmission capacity hungry representation processor Older transport interfaces, for example, AMBA AHB 2.0, does not bolster pipelining or byte empowers.

Slide 11

Bus Interface Verification Environment Two confirmation situations (Arbiter/Master, Input/Slave)

Slide 12

OCP Design and Verification Project Conclusions Good components Pipelining Byte empowers Good parameterised approach Customer subordinate arrangements Only important elements are executed Simple to outline and check Cycle from client prerequisites to plan and confirmation is short Fewer bugs because of effortlessness

Slide 13

Future Trends in Mobile Graphics Acceleration Display determination sizes will be bigger and of higher quality This is the reason illustrations processor innovation must be versatile not to build the memory data transfer capacity an excessive amount of when presentation resolutions expand So called "prompt mode rendering" is utilized as a part of Bitboys\' items and this will be the key issue as far as memory transmission capacity It is additionally simple to scale the reserves of the representation processor or the transport engineering OCP 2.0 shows effectively great elements, which are required in bleeding edge interactive media innovation

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