4-Bit Number juggling Rationale Unit (ALU) with Convey Look Ahead Snake.

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2. Motivation. AbstractSpecificationsIntroductionALU OperationsDesign FlowDesign IssuesSchematicsLessons LearnedSimulation ResultsConclusions. 3. Conceptual. Effectively composed a 4-bit ALU with Carry Look Ahead Adder by utilizing Cadence CAD devices. The whole venture is composed towards AMI06 (0.6mm) process particular. The outline has effectively passed DRC and LVS, and met the coveted 200MHz
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4-Bit Arithmetic Logic Unit (ALU) with Carry Look Ahead Adder Keli Wu Eng Boon Chong Li Chun Sum Yeung Advisor: David Parent May 2005

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Agenda Abstract Specifications Introduction ALU Operations Design Flow Design Issues Schematics Lessons Learned Simulation Results Conclusions

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Abstract Successfully composed a 4-bit ALU with Carry Look Ahead Adder by utilizing Cadence CAD apparatuses. The whole venture is outlined towards AMI06 (0.6 m) process detail. The configuration has effectively passed DRC and LVS, and also met the coveted 200MHz clock velocity, force and region imperatives.

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4-bit ALU Specifications The planned ALU meets the accompanying determinations: Able to perform 4 Logic Operations and 8 Arithmetic Operations Operating Frequency: 200MHz Output DFF must have the capacity to drive 30fF.

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Introduction An Arithmetic Logic Unit (ALU) is the crucial unit of any processing framework. It is part of the computerized PC equipment in which number juggling and rationale operations are played out The ALU planned can deal with two 4-bit contributions to create a required yield in light of the yield selector line. The complete rundown of the conceivable yields capacities are as recorded in the accompanying tables.

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ALU Operations

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Design Flows Create Schematics and formats for Nand, Nor, Xor, Carry Generators, Adder, flip-failure, and Mux in the Cadence device. Test the schematics rationale of every modules by utilizing NCVerilog. Fell the above single piece parts to shape 4-bit parts. Collected all the 4-bit parts together. Run the DRC, separated and LVS check to confirm the configuration. Investigated the circuit power and timing by utilizing Affirma.

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Design Issues Implementation of long Boolean expressions for Carry Generators. Breakdown rationale level as opposed to utilizing AOI. 21 rationale levels, requires bigger gadgets for speedier spread postponement per rationale level. Transistors are estimated to have the same measurements with the goal that they fit together pleasantly. The conservative format requires watchful thought for sign steering.

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4 Bit ALU Schematic

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Verification-LVS Check

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Logic Simulation Input A: 1000 Input B: 1T00

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Power Simulation Power = 18.7 mW (Only the longest way, around 15% of the circuit, is exchanging.)

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Lessons Learned Don\'t course in Poly Fix the LVS Error Use chain of command methodology Optimize transistor size to meet particular. Essential force steering.

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Conclusions Our task has 1176 transistors and 21 terminals. The zone of our outline is around 390 m X 360 m. The force is roughly 131mW. The circuit can work up to 250MHz.

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Acknowledgments Thanks to teacher David Parent for his direction and help all through the venture. Because of Cadence Design Systems for the VLSI Lab.

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