68000 Interface Timing Diagrams .


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68000 Read Cycle. 68000 read word from memory68000 goes about as transport masterinitiates readMemory goes about as transport slaveresponds to ace requestsMemory-mapped I/O
Transcripts
Slide 1

Plot 68000 Read Cycle 68000 Write Cycle Goal Understand 68000 transport cycles Learn how to join memory, peripherals to CPU Reading Microprocessor Systems Design, Clements, Ch. 4 68000 Interface Timing Diagrams

Slide 2

68000 read word from memory 68000 goes about as transport ace starts read Memory goes about as transport slave reacts to ace solicitations Memory-mapped I/O "memory" can truly be fringe gadget Interlocked handshaking amongst ace and slave ace uses R/~W, AS*, UDS*, LDS* to tell memory that address is available slave utilizes DTACK* to tell CPU that information is prepared A 68000 memory get to takes at least eight clock states numbered from clock states S0 to S7 68000 Read Cycle

Slide 3

Not to scale - connections more essential Typically couldn\'t care less about information/address flag values Do think about control flag values Voltage detecting V ol - greatest legitimate zero voltage on yield V goodness - least consistent one voltage on yield V il - greatest sensible zero voltage on information V ih - least coherent one voltage on info Time defers measured from reference voltage half, 10%, 90% of V dd Timing Diagrams

Slide 4

A memory get to starts in clock state S0 and finishes in state S7

Slide 5

The most vital parameter of the clock is the length of a cycle, t CYC .

Slide 6

At the begin of a memory get to the CPU sends the address of the area it wishes to peruse to the memory

Slide 7

We are occupied with when the 68000 produces another address for use in the present memory get to The following slide demonstrates the relationship between the new address and the condition of the 68000\'s clock Address Timing

Slide 8

In state S1 another address gets to be distinctly legitimate for the rest of the memory get to Initially, in state S0 the address transport contains the old address

Slide 9

The time at which the substance of the address transport change can be identified with the edges of the clock.

Slide 10

Let\'s take a gander at the grouping of occasions that oversee the planning of the address transport The "old" address is evacuated in state S0 The address transport is glided for a brief timeframe, and the CPU puts out another address in state S1 Address Timing

Slide 11

The old address is expelled in clock state S0 and the address transport coasted

Slide 12

t CLAV The creator is keen on the time when the address first gets to be distinctly substantial. This point is t CLAV seconds after the falling edge of S0.

Slide 13

The memory has to know when the address from the CPU is legitimate. An address strobe, AS*, is stated to show that the address is legitimate.

Slide 14

We are occupied with the relationship between the time at which the address is legitimate and the time at which the address strobe, AS*, is attested When AS* is dynamic low it demonstrates that the address is substantial We now take a gander at the planning of the clock, the address, and the address strobe Address and Address Strobe

Slide 15

AS* goes dynamic low after the address has turned out to be legitimate AS* goes idle high before the address changes

Slide 16

AS* goes low in clock state S2

Slide 17

The 68000 has two information strobes LDS* and UDS*. These select the lower byte or the upper byte of a word amid a memory access To keep things straightforward, we will utilize a solitary information strobe, DS* The planning of DS* in a read cycle is the same as the address strobe, AS* The Data Strobes

Slide 18

The information strobe, is declared in the meantime as AS* in a read cycle

Slide 19

During a read cycle the memory furnishes the CPU with information The following slide demonstrates the information transport and the planning of the information flag Note that substantial information does not show up on the information transport until close to the finish of the read cycle The Data Bus

Slide 20

Data from the memory shows up close to the finish of the read cycle

Slide 21

We are going to redraw the planning outline to expel mess We aren\'t keen on the flag ways themselves, just in the relationship between the signs Analyzing the Timing Diagram

Slide 22

We are occupied with the relationship between the clock, AS*/DS* and the information in a read cycle

Slide 23

The soonest time at which the memory can start to get to information is measured from the time when the address is first legitimate

Slide 24

Data gets to be distinctly substantial Address gets to be distinctly substantial The time between address legitimate and information legitimate is the memory\'s get to time, t acc

Slide 25

We have to ascertain the memory\'s get to time By knowing the get to time, we can utilize the fitting memory segment Equally, on the off chance that we select a given memory segment, we can figure whether its get to time is satisfactory for a specific framework Calculating the Access Time

Slide 26

Data from the memory is hooked into the 68000 by the falling edge of the check in state S6.

Slide 27

Data must be legitimate t DICL seconds before the falling edge of S6

Slide 28

We realize that the time between the address substantial and information substantial is t acc

Slide 29

The address gets to be distinctly substantial t CLAV seconds after the falling edge of S0

Slide 30

From the falling edge of S0 to the falling edge of S6: the address gets to be distinctly substantial the information is gotten to the information is caught

Slide 31

The falling edge of S0 to the falling edge of S6 is three clock cycles

Slide 32

3 t cyc = t CLAV + t acc + t DICL

Slide 33

68000 clock 8 MHz t CYC = 125 ns 68000 CPU t CLAV = 70 ns 68000 CPU t DICL = 15 ns What is the base t acc ? 3 t CYC = t CLAV + t acc + t DICL 375 = 70 + t acc + 15 t acc = 290 ns Timing Example

Slide 34

Timing spec references nonconcurrent signals for memory activities Spec references clock for CPU activities CPU yields change CPU tests inputs Metastability consider the possibility that information changes at same time clock tests it. abuses setup and hold time determinations once in a while result is unclear infrequently spec says hold up a check cycle practically speaking info rationale can go into metastable state in the middle of 0 and 1 cause other rationale to come up short plan to keep away from this circumstance 68000 Synch/Asynch System

Slide 35

Features deliver decoder to choose RAM 4KB piece adjusted to 4KB limit utilize chip select for byte read/compose alternatively delay DTACK Chip select 68000 Connected to 6116P-6 SRAM Inputs Outputs Operation AS* RAMCS* UDS* LDS* CS2* CS1* 1 X X X 1 1 Noop X 1 X X 1 1 Noop 0 0 0 0 0 0 Word 0 0 0 1 0 1 Upper byte 0 0 1 0 1 0 Lower byte 0 0 1 1 1 1 Noop

Slide 36

Relate 68000 planning graph to 6116P outline Memory get to S0 tumble to S6 fall = 3 x t CYC address gets to be distinctly legitimate (t CLAV ), memory got to (t AA ), information setup (t DICL ) add up to memory address get to time = t CLAV + t AA + t DICL Memory read for 8 MHz 68000 3 x t CYC > t CLAV + t AA + t DICL t AA < 3 x t CYC - t CLAV - t DICL t AA < 3 x 125 - 70 - 15 = 290 ns 6116P has t AA < 200 ns, so zero sit tight states Memory read for 12.5 MHz 68000 t AA < 3 x 80 - 55 - 10 = 175 ns need to include a hold up state Read Cycle Calculations

Slide 37

Data hold time t SHDI > 0 ns from rising AS* address does not change until rising S0 rising AS*/UDS*/LDS* deselects chip deselect to drifting (t CHZ ) > 0 ns door delays guarantee spec Chip select/deselect time CS* from AS*, RAMCS*, USD*/LDS* if address decipher < 30 ns, then CS* one entryway delay after AS* CS* to driver on < 15 ns, much sooner than information accessible information transport skimmed t CLSH + t GATE + t CHZ after S7 begins if t GATE = 10 ns, transport glides 70 + 10 + 60 = 140 ns after S7, S0 = 62.5 ns, transport could coast 15 ns into S1 affirm since next access in S2 Read Cycle Calculations (cont.)

Slide 38

Similar to peruse cycle Difference CPU puts information on information transport right on time in transport cycle UDS*/LDS* not attested until information on transport R/~W is set low most memory needs address stable before this memory/fringe peruses information can utilize UDS*/LDS* to hook information into memory Timing necessities regularly compose cycle specs can be effectively met recollections compose speedier than they read enormous driver to little cell versus little cell to huge load 68000 Write Cycle

Slide 39

Used for unbreakable operations locks, semaphores, screens TAS - test and set CAS/CAS2 - look at and swap 68000 keeps address strobe low address transport esteem same for read and compose strobes information for read and compose set R/~W high, then low Read-Modify-Write Cycle

Slide 40

Synchronous transport I/O gadgets and memory likewise referenced to clock Much less difficult planning Many less clock cycles per transport exchange Everything referenced to clock See Section 7.5 See ColdFire User\'s Manual pg. 17-10 68040 & ColdFire Timing

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