8-11-2007.


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Circulation - assignments coordinate in numerous registering destinations ... Intel x86 family have the same fundamental structural engineering. The IBM System/370 family share the ...
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8-11-2007 (Lecture 2) CS8421 Computing Systems Dr. Jose M. Garrido Class Will Start Momentarily…

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Vehicle frameworks Traffic control Process control Medical frameworks Military RT frameworks Manufacturing Robots frameworks Security control Telecommunication frameworks Computer amusements Multimedia frameworks Household apparatus checking & control Building vitality control Real-Time Applications and Examples

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Properties of Real-Time Systems Timeliness - the framework must perform operations in auspicious way Reactiveness - the framework persistently reacts to (irregular) occasions Concurrency - numerous concurrent exercises are completed Distribution - undertakings participate in various registering locales

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RTS Time Issues The objective is to diminish two particular interims: administration time - the interim taken to figure a reaction to a given information inactivity - the interim between the season of event of an information and the time at which it begins being overhauled The whole of these two interims speaks to the reaction time . This must be shorter than the due date for this kind of information.

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Architecture alludes to the ascribes unmistakable to the developer Instruction set Number of bits utilized for information representation I/O systems Addressing methods. Is there an increase guideline?

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Organization alludes to how components are actualized Control signals Interfaces Memory innovation. Is there an equipment increase unit or is it done by rehashed expansion?

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Architecture & Organization All Intel x86 family have the same fundamental engineering The IBM System/370 family have the same essential design This gives code similarity At slightest in reverse Organization contrasts between various adaptations

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Structure & Function Structure is the path in which segments identify with each other Function is the operation of individual segments as a major aspect of the structure

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Computer Architecture Overview Components of a PC framework: CPU Main Memory Secondary Storage I/O Devices Bus Operating System

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General System Structure

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Computer Functions The PC capacities are: Data preparing Data stockpiling (memory) Data development (I/O) Control

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Computer Functional View

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Data Movement

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Data Storage

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Processing from/to Storage

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Processing from Storage to I/O

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Structure - Top Level Computer Peripherals Central Processing Unit Main Memory Computer Systems Interconnection Input Output Communication lines

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Structure - The CPU Arithmetic and Logic Unit Computer Registers I/O System Bus CPU Internal CPU Interconnection Memory Control Unit

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Structure - The Control Unit Control Unit CPU Sequencing Logic ALU Control Unit Internal Bus Control Unit Registers and Decoders Registers Control Memory

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ENIAC - foundation Electronic Numerical Integrator And Computer Eckert and Mauchly University of Pennsylvania Trajectory tables for weapons Started 1943 Finished 1946 Too late for war exertion Used until 1955

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ENIAC - Details Decimal (not parallel) 20 gatherers of 10 digits Programmed physically by switches 18,000 vacuum tubes 30 tons 15,000 square feet 140 kW power utilization 5,000 augmentations for every second

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von Neumann/Turing Stored Program idea Main memory store projects and information ALU working on paired information and double code Control unit translating guidelines from memory and executing Input and yield gear worked by control unit Princeton Institute for Advanced Studies IAS Completed 1952

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Structure of von Neumann Machine

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IAS - subtle elements 1000 x 40 bit words Binary number 2 x 20 bit directions Set of registers (stockpiling in CPU) Memory Buffer Register Memory Address Register Instruction Register Instruction Buffer Register Program Counter Accumulator Multiplier Quotient

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Structure of IAS – point of interest

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Functioning of the IAS Computer Repetitively playing out a guideline cycle A direction cycle has two subcycles Fetch cycle – the "opcode" of guideline and its location are stacked into registers IR and MAR Execute cycle - elucidation of the "opcode" and execution of the direction

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Instructions of the IAS Computer The IAS PC had 21 directions These directions are assembled as: Data exchange Unconditional branch Conditional branch Arithmetic Address adjust

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Commercial Computers 1947 - Eckert-Mauchly Computer Corporation UNIVAC I (Universal Automatic Computer) US Bureau of Census 1950 computations Became a portion of Sperry-Rand Corporation Late 1950s - UNIVAC II Faster More memory

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IBM Punched-card handling hardware 1953 - the 701 IBM\'s initially put away program PC Scientific figurings 1955 - the 702 Business applications Lead to 700/7000 arrangement The IBM 7094 presented the information channel, a littler particular I/O processor

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Transistors Replaced vacuum tubes Smaller Cheaper Less warmth dissemination Solid State gadget Made from Silicon (Sand) Invented 1947 at Bell Labs William Shockley et al.

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Transistor Based Computers Second era machines NCR & RCA delivered little transistor machines IBM 7000 DEC - 1957 Produced PDP-1

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Microelectronics Literally - "little gadgets" A PC is comprised of entryways, memory cells and interconnections These can be fabricated on a semiconductor e.g. silicon wafer Used in the third era of PCs

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Generations of Electronics Vacuum tube - 1946-1957 Transistor - 1958-1964 Small scale combination - 1965 on Up to 100 gadgets on a chip Medium scale coordination - to 1971 100-3,000 gadgets on a chip Large scale mix - 1971-1977 3,000 - 100,000 gadgets on a chip Very expansive scale joining - 1978 to date 100,000 - 100,000,000 gadgets on a chip Ultra extensive scale mix Over 100,000,000 gadgets on a chip

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Moore\'s Law Increased thickness of segments on chip Gordon Moore - fellow benefactor of Intel Number of transistors on a chip will twofold consistently Since 1970\'s advancement has moderated somewhat Number of transistors copies like clockwork Cost of a chip has remained practically unaltered Higher pressing thickness implies shorter electrical ways, giving higher execution Smaller size gives expanded adaptability Reduced power and cooling necessities Fewer interconnections builds unwavering quality

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Growth in CPU Transistor Count

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IBM 360 arrangement 1964 Replaced (& not perfect with) 7000 arrangement First arranged "family" of PCs Similar or indistinguishable guideline sets Similar or indistinguishable O/S Increasing velocity Increasing number of I/O ports (i.e. more terminals) Increased memory size Increased cost Multiplexed switch structure

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DEC PDP-8 1964 First minicomputer Did not require aerated and cooled room sufficiently small to sit on a lab seat $16,000 $100k+ for IBM 360 Embedded applications & OEM BUS STRUCTURE

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DEC - PDP-8 Bus Structure I/O Module Main Memory I/O Module Console Controller CPU OMNIBUS

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Semiconductor Memory 1970 Fairchild Size of a solitary center i.e. 1 bit of attractive center stockpiling Holds 256 bits Non-damaging read Much speedier than center Capacity roughly pairs every year

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Intel 1971 - 4004 First microchip All CPU segments on a solitary chip 4 bit Followed in 1972 by 8008 8 bit Both intended for particular applications 1974 - 8080 Intel\'s first broadly useful microchip

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Improving Speed Pipelining On load up reserve On load up L1 & L2 store Branch forecast Data stream investigation Speculative execution

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Performance Mismatch Processor speed expanded Memory limit expanded Memory speed falls behind processor speed

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DRAM and Processor Characteristics

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Trends in DRAM use

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Pentium Evolution (1) 8080 first universally useful chip 8 bit information way Used in first PC – Altair 8086 a great deal all the more intense 16 bit direction store, prefetch couple of guidelines 8088 (8 bit outer transport) utilized as a part of first IBM PC 80286 16 Mbyte memory addressable up from 1Mb 80386 32 bit Support for multitasking

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Pentium Evolution (2) 80486 complex capable reserve and direction pipelining worked in maths co-processor Pentium Superscalar Multiple guidelines executed in parallel Pentium Pro Increased superscalar association Aggressive register renaming branch expectation information stream examination theoretical execution

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Pentium Evolution (3) Pentium II MMX innovation representation, video & sound preparing Pentium III Additional gliding point guidelines for 3D illustrations Pentium 4 Note Arabic as opposed to Roman numerals Further skimming point and mixed media upgrades Itanium 64 bits

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PowerPC IBM, Motorola, Apple Used in Apple Macintosh RISC design 601 603 604 620 740/750 (G3) G4 G5

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What is a Program? A succession of steps (guidelines?) For every progression, a number juggling or sensible operation is done For every operation, an alternate arrangement of control signs is required

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Function of Control Unit For every operation a remarkable operation code is given e.g. Include, MOVE An equipment portion acknowledges the code and issues the control flags This is the establishment for a PC!

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Components The Control Unit and the Arithmetic and Logic Unit constitute the Central Processing Unit Data and directions need to get into the framework and results out Input/yield Temporary stockpiling of code and results is required Main memory

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Components: Top Level View

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Instruction Cycle Two stages: Fetch Execute

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Fetch Cycle Program Counter (PC) holds location of next guideline to get

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