Address 8 Memory Components and Timing.


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Address 8 Memory Components and Timing. Hai Zhou ECE 303 Progressed Advanced Outline Spring 2002. Diagram. Consecutive rationale systems Locks (RS Hook) Flip-flops (D and JK) Timing issues (setup and hold times) Perusing: Katz 6.1, 6.2, 6.3, Dewey 8.1, 8.2. Consecutive Exchanging Systems.
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Slide 1

Address 8 Memory Elements and Clocking Hai Zhou ECE 303 Advanced Digital Design Spring 2002 ECE C03 Lecture 8

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Outline Sequential rationale systems Latches (RS Latch) Flip-flops (D and JK) Timing issues (setup and hold times) READING: Katz 6.1, 6.2, 6.3, Dewey 8.1, 8.2 ECE C03 Lecture 8

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Sequential Switching Networks Circuits with Feedback: Some yields are additionally inputs Traffic Light Controller is a complex successive rationale system Sequential rationale frames premise for building "memory" into circuits These memory components are primitive consecutive circuits ECE C03 Lecture 8

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Simple Circuits with Feedback Primitive memory components made from fell doors Simplest entryway segment: inverter Basis for business static RAM plans Cross-coupled NOR doors and NAND doors likewise conceivable "1" Cascaded Inverters: Static Memory Cell "0" LD Selectively break criticism way to stack new esteem into cell \LD A Z LD ECE C03 Lecture 8

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RS Latch R S Q \ Q Just like fell inverters, with capacity to compel yield to 0 (reset) or 1 (set) R S R Q S \Q Timing Waveform 100 Reset Hold Reset Set Race Set Forbidden State Forbidden State ECE C03 Lecture 8

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State Behavior of RS Latch Q 1 0 1 0 Truth Table Summary of R-S Latch Behavior 1 ECE C03 Lecture 8

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Theoretical RS Latch State Diagram Q SR = 00, 10 SR = 00, 01 SR = 1 0 1 0 1 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 SR = 1 0 SR = 0 1 SR = 1 0 SR = 0 SR = 0, 11 1 ECE C03 Lecture 8

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Observed RS Latch Behavior Q SR = 00, 10 SR = 00, 01 SR = 1 0 1 0 1 SR = 0 1 SR = 0 1 SR = 1 0 SR = 11 SR = 1 SR = 1 0 SR = 0 SR = 0 Very hard to watch R-S Latch in the 1-1 state Ambiguously comes back to state 0-1 or 1-0 An alleged "race condition" ECE C03 Lecture 8

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Definition of Terms in Clocking T su h Clock: Periodic Event, reasons condition of memory component to change rising edge , falling edge , abnormal state , low level Input Setup Time (Tsu) Minimum time before the timing occasion by which the information must be steady Clock There is a timing "window" around the timing occasion amid which the data must stay steady and unaltered keeping in mind the end goal to be perceived Hold Time (Th) Minimum time after the timing occasion amid which the information must stay stable ECE C03 Lecture 8

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Level Sensitive RS Latch \ S \ Q \ R Level-Sensitive Latch otherwise known as Gated R-S Latch Schematic: Q \enb Timing Diagram: \S \R \enb Q \Q ECE C03 Lecture 8

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Latches versus Flip-failures Input/Output Behavior of Latches and Flipflops Type When Inputs are Sampled When Outputs are Valid unclocked dependably engendering postponement from lock info change level clock high proliferation delay from delicate (Tsu, Th around data change hook falling clock edge) positive edge clock lo-to-hello move spread deferral from flipflop (Tsu, Th around rising edge of clock rising clock edge) negative edge clock hey to-lo move engendering postponement from flipflop (Tsu, Th around falling edge of clock falling clock edge) expert/slave clock greetings to-lo move spread postponement from flipflop (Tsu, Th around falling edge of clock falling clock edge) ECE C03 Lecture 8

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Latches versus Flipflops Positive edge-activated flip-lemon Level-touchy lock 7474 D Q Edge activated gadget test inputs on the occasion edge Transparent locks test inputs the length of the clock is affirmed Clk Timing Diagram: 7476 D Q D C Clk Q 7474 Bubble here for negative edge activated gadget Q 7476 Behavior the same unless data changes while the clock is high ECE C03 Lecture 8

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Timing Specifications of FFs T su h su h 20 5 20 5 ns T w 25 ns T plh phl 25 ns 40 ns 13 ns 25 ns 74LS74 Positive Edge Triggered D Flipflop D • Setup time • Hold time • Minimum clock width • Propagation postponements (low to high, high to low, max and run of the mill) Clk Q All estimations are produced using the timing occasion that is, the rising edge of the clock ECE C03 Lecture 8

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Timing Specifications of Latches T su h su h 20 5 20 5 ns T w 20 ns T plh phl C » Q C » Q 27 ns 25 ns 15 ns 14 ns T plh phl D » Q D » Q 27 ns 16 ns 15 ns 7 ns 74LS76 Transparent Latch D • Setup time • Hold time • Minimum Clock Width • Propagation Delays: high to low, low to high, greatest, ordinary information to yield clock to yield Clk Q Measurements from falling clock edge or rising or falling information edge ECE C03 Lecture 8

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RS Latch Revisited Q ( t ) Truth Table: Next State = F(S, R, Current State) Derived K-Map: S SR S(t) R(t) Q(t) Q(t+d) 0 HOLD 0 1 - - 0 1 0 RESET 0 1 0 - - 1 0 1 SET 1 0 1 - - 1 0 X NOT ALLOWED 1 X 00 01 11 10 0 X 1 0 X 1 R Characteristic Equation: Q+ = S + R Q t S R-S Latch Q+ R Q ECE C03 Lecture 8

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JK Latch Design \ Q \ Q R-S hook How to take out the taboo state? K R J(t) K(t) Q(t) Q(t+d) 0 HOLD 0 1 - - 0 1 0 RESET 0 1 0 - - 1 0 1 SET 1 0 1 - - 1 0 1 TOGGLE 1 0 J S Q Idea: utilization yield criticism to ensure that R and S are never both one J, K both one yields switch Characteristic Equation: Q+ = Q K + Q J ECE C03 Lecture 8

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JK Latch Race Condition J K Q \ Q Reset Set Toggle 100 Race Condition Toggle Correctness: Single State change per timing occasion Solution: Master/Slave Flipflop ECE C03 Lecture 8

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Solution: Master Slave JK Flip Flop R-S R-S Latch 1\'s Catch T oggle J K Clk P Master yields \ P Q Slave \ Q yields Master Stage Slave Stage \Q K \P \Q R \Q S Q S Q P J Q Clk Sample inputs while clock low Sample inputs while clock high Uses time to break input way from yields to inputs! Set Reset 100 Correct Toggle Operation ECE C03 Lecture 8

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Positive versus Negative Edge Triggered Devices D Clk Q pos Positive edge-t riggered FF \ Q pos Q neg Negative edge-t riggered FF \ Q neg 100 Positive Edge Triggered Inputs inspected on rising edge Outputs change in the wake of rising edge Negative Edge Triggered Inputs tested on falling edge Outputs change in the wake of falling edge Toggle Flipflop Formed from J-K with both inputs wired together ECE C03 Lecture 8

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Realizing Circuits with Different Kinds of FFs R-S Clocked Latch: utilized as capacity component as a part of restricted width timed frameworks its utilization is not suggested! notwithstanding, major building square of other flipflop sorts J-K Flipflop: flexible building piece can be utilized to actualize D and T FFs typically obliges slightest measure of rationale to execute ƒ(In,Q,Q+) yet has two inputs with expanded wiring unpredictability in view of 1\'s getting, never utilize expert/slave J-K FFs edge-activated assortments exist D Flipflop: minimizes wires, tremendously favored in VLSI advances least complex configuration procedure best decision for capacity registers T Flipflops: don\'t generally exist, developed from J-K FFs normally best decision for executing counters Preset and Clear inputs very alluring!! ECE C03 Lecture 8

Slide 21

Timing Methodology • Set of tenets for interconnecting parts and timekeepers • When taken after, insurance fitting operation of framework • Approach relies on upon building pieces utilized for memory components For frameworks with locks: Narrow Width Clocking Multiphase Clocking (e.g., Two Phase Non-Overlapping) For frameworks with edge-activated flipflops: Single Phase Clocking • Correct Timing: (1) right inputs, as for time, are given to the FFs (2) no FF changes more than once per timing occasion ECE C03 Lecture 8

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Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register S,R are preset, preclear New esteem to first stage while second stage acquires current estimation of first stage IN Q0 Q1 D Q D Q C Q C Q CLK Correct Operation, accepting positive edge activated FF ECE C03 Lecture 8

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Why Cascaded Flip-Flops Work T su 20 ns 20 ns Q 0 T plh 13 ns 13 ns Q 1 T h 5 ns 5 ns • Propagation delays far surpass hold times; Clock width limitation surpasses setup time • This assurances taking after stage will hook current quality before it is supplanted by new esteem • Assumes boundlessly quick circulation of the check In Timing imperatives ensure legitimate operation of fell segments Clk ECE C03 Lecture 8

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