Another PAGE TABLE FOR 64-BIT ADDRESS SPACES.


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THE PROBLEM. Programs\' memory use copies each maybe a couple years.Most processor architectures are presently moving from 32-bit to 64-bit virtual location spacesHow would current page table associations scale up?Will bolster vast however meagerly populated location spaces. CURRENT ORGANIZATIONS (I).
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A NEW PAGE TABLE FOR 64-BIT ADDRESS SPACES M. Talluri, M. D. Slope, Y. A. Kalidi University of Wisconsin, Madison Sun Microsystems Laboratories

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THE PROBLEM Programs\' memory use copies each maybe a couple years. Most processor designs are presently moving from 32-bit to 64-bit virtual address spaces How might current page table associations scale up? Will bolster extensive however meagerly populated address spaces

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CURRENT ORGANIZATIONS (I) Three primary methodologies: Linear page tables : PTs are too expansive to be put away in fundamental memory Store PT in virtual memory (VMS arrangement) Very substantial page tables require more than 2 levels (3 levels on MIPS R3000)

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CURRENT ORGANIZATIONS (II) Forward-mapped page tables: < Page Number > 1ary 2ary Offset Virtual Address MASTER INDEX SUBINDEX (unaltered) Frame Addr . Counterbalanced Frame No Physical Address

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hash VPN PPN CURRENT ORGANIZATIONS (III) Hashed (reversed) page tables : VPN = virtual page number PPN = "physical page" number = page outline number

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What isn\'t right with them? None of these arrangements scales up to 64-bit addresses: Linear and forward-mapped page tables require an excessive number of levels Hashed page tables require a lot of space: Must store the VPN and the following pointer notwithstanding PPN

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CLUSTERED PAGE TABLES Variant of hashed page tables Each section stores mapping data for a bunch of continuous page table passages Number of pages in a group is known as the grouping component .

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How they work hash VPN PPN0 PPN1 Clustering variable = 2 Each passage maps 2 adjoining VPNs

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Advantages of grouped PTs Require a great deal less space overhead: just a single VPN and one next pointer for every bunch Take preferred standpoint of the way that the address space of many projects comprises of little groups of pages Interact much better with the TLB miss taking care of firmware or programming.

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Are we truly sparing space? Accept a grouping element of 2 Each passage maps 2 pages and possesses 4×8 bytes VPN PPN0 PPN1

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The reply Without bunching, every section maps one page and involves 3×8 bytes Clustering will spare space if more than 67% of the page mappings are valuable VPN PPN

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HANDLING TLB MISSES Page table association ought to permit productive treatment of TLB misses by firmware (traditional arrangement) programming (MIPS, Alpha, UltraSPARC) Should handle two late TLB progresses subblocking superpages

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Subblocking Associates different physical page numbers (PPN\'s) with each TLB label: C omplete subblocking permits the page outlines containing the subblock pages to be anyplace in primary memory (MIPS 4X00x) Partial subblocking requires these page casings to be put in a solitary, adjusted piece of fundamental memory; there is one PPN per TLB tag.

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Handling complete subblocking Have bunch size of PT equivalent to subblocking component hash VPN PPN0 PPN1

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Handling fractional subblocking Since all page edges are touching, have a solitary PPN per group Bitmap ( bm ) demonstrates which pages are in memory hash VPN VPN0 PPN0 bm

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Note Each page table passage maps two virtual pages into two physical pages Virtual page VPN0 is mapped into physical page PPN0 Virtual page VPN0 + 1 is mapped into physical page PPN0 + 1 These mappings are legitimate i f the virtual page is really in fundamental memory

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Problem A virtual memory framework has 64-bit addresses and a bunched page table with a grouping element of 4. In the event that every address possesses 8 bytes, what might be the length of a page table section for: (an) incomplete subblocking ? (b) finish subblocking ?

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Hint No extra space is required for bitmap If page size is equivalent to 2 p , page size will involve 64 - p bits by and by, page measure > 1,024 and p > 10 Can utilize these p bits to store the bitmap

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Solution (I) With finish subblocking , each PTE has: one virtual page number four physical page numbers one pointer to next section 6 passages × 8 bytes = 48 bytes

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Solution (II) With fractional subblocking , each PTE has: one virtual page number one physical page number four bits of bitmap one pointer to next section 3 sections × 8 bytes = 24 bytes

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Superpages Sets of pages that are adjusted both in virtual and in physical memory Brought in memory and out of memory as a solitary element Size is a force of-two numerous of the page estimate (MIPS, UltraSPARC, Alpha, PowerPC) Large superpages (256KB or more) are particularly valuable for bit information

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Handling superpages (I) We can: Have one PTE for every page in the superpage Simplest arrangement yet does not spare space Have one page table for each superpage estimate (counting confined pages) Each page miss will now need to look a few PTs

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Handling superpages (II) S tore superpage mappings at the suitable level of a PT Only works with multi-level PTs having a tree structure Pick hash capacity to such an extent that all pages that are in the same superpage are in a similar basin Results in bigger cans and longer ventures

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Handling superpages (III) Best arrangement is by all accounts Use same information structures for little superpages and halfway subblocks Otherwise have one section for every bunch in the superpage Support huge superpages on a specially appointed premise There will be not very many of them

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CONCLUSIONS 64-bit locations will drive a reexamining of page table association New associations must bolster productive treatment of TLB misses Supporting incomplete subblocking is most vital issue since incomplete subblocking requires less complex OS bolster than superpages and lessens all the more adequately page table sizes

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