Chap 6. Successive Circuits.

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Description Chap.6. 2. 6-1 Sequential Circuit Definitions. successive circuit ... yields are a component of the inputs and current situation with the capacity components. next state ...
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Chap 6. Consecutive Circuits Spring 2004 Jong Won Park

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6-1 Sequential Circuit Definitions successive circuit combinational circuit + capacity components stockpiling components store paired data condition of the successive circuit at given state yields are an element of the sources of info & current situation with the capacity components next condition of capacity components is likewise an element of the data sources & the present state Figure 6-1 Block Diagram of a Sequential Circuit

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6-1 Sequential Circuit Definitions Figure 6-2 rationale Structures for Strong Information

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6-1 Sequential Circuit Definitions two sorts synchronous consecutive circuit conduct is characterized from the learning of its signs at discrete moments of time offbeat consecutive circuit conduct relies on upon the contributions at any case of time & the request in persistent time in which the sources of info change, clock generator synchronous successive circuit has a planning gadget create an occasional prepare of clock heartbeats stockpiling components are influenced just upon the landing of every heartbeat clock heartbeats are connected with different signs the yields can change their esteem just within the sight of clock heartbeats timed successive circuits

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6-1 Sequential Circuit Definitions flip-slump stockpiling components utilized in timed consecutive circuits a twofold stockpiling gadget equipped for putting away one piece of information Normally, a successive circuit utilizes numerous flip-tumbles the move from one state to alternate happens just at foreordained time interims managed by the clock beats two yields: typical & supplemented values Figure 6-3 Synchronous Clocked Sequential Circuit

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6-2 Latches A capacity component can keep up a parallel state inconclusively until guided by an info flag to switch states Latch most essential sorts of flip-lemon basic & frequently utilized inside flip-flops utilized with more intricate timing techniques to execute consecutive circuits SR Latch a circuit with 2 cross-coupled NOR (or NAND) doors 2 inputs: S (set) & R (reset)

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6-2 Latches if S=1, Q=1 (Q\'=0); if R=1, Q=0 (Q`=1) if S=R=0, keep past state (hold) if S=R=1, indistinct state Figure 6-4 SR Latch with NOR Gates Figure 6-5 Logic Simulatiom Of SR Latch Behavior

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6-2 Latches S\'R\' hook with two cross-coupled NAND entryways the info signals for the NAND require the supplement of those qualities utilized for the NOR Figure 6-6 S\'R\' Latch with NAND Gates

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6-2 Latches SR lock with a control information a fundamental S\'R\' lock with 2 NAND doors C (control input) goes about as an empower motion for the other 2 inputs if C=0, no activity; if C=1, go about as SR f-f the vague condition (S=R=1) ==> sometimes utilized as a part of practice however critical, all others are built from it SR hook with control information is called SR (or RS) f-f Figure 6-7 SR Latch with Control Input

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6-2 Latches D Latch dispense with the undesirable state of the uncertain state make S & R never equivalent to 1 in the meantime ==> incorporate an inverter 2 inputs: D (information) & C (control) D goes to S; D\' goes to R go about as a brief stockpiling developed with transmission entryways Figure 6-8 D Latch Figure 6-9 D Latch with Transmission Gates

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6-3 Flip-Flops the condition of a hook is permitted to switch by a transitory change of the control unit a fleeting change is known as a trigger a successive circuit has an input way control beat goes to rationale 1 the new condition of a lock may show up the yield is associated with the info ...…  Form a solid flip-flounder ace slave flip-slump & edge-activated flip-flounder

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6-3 Flip-Flops Master-Slave Flip-Flop Figure 6-10 SR Master-Slave Flip-Flop Figure 6-11 Logic Simulation of a SR Master-Slave Flip-Flop

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6-3 Flip-Flops Figure 6-12 Negative Edge-Triggered D Flip-Flop

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6-3 Flip-Flops Edge-Triggered Flip-tumble disregard the beat while it is at a consistent level, but triggers just amid the move of the clock flag Figure 6-13 Positive-Edge-Triggered D Flip-Flop

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6-3 Flip-Flops Standard Graphics Symbols Figure 6-14 Standard Graphics Symbols for Latches and Flip-Flops

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6-3 Flip-Flops Direct Inputs Preset and Clear information sources very attractive !! Figure 6-15 D Flip-Flop with Direct Set and Reset

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4.3 Flip-Flops Flip-Flop Timing Figure 6-16 Flip-Flop Timing Parameters

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6-4 Sequential Circuit Analysis conduct of a successive circuit is resolved from inputs, yields, & current situation with the circuit yields & the following state are capacity of sources of info & display state Input Equations a rationale chart of consecutive circuit incorporates F-Fs (any type), or combinational circuit the part of the combinational circuit can be portrayed by an arrangement of Boolean capacities, called input conditions

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6-4 Sequential Circuit Analysis Sequential Circuit Analysis Logic outline Input conditions and yield conditions State table State outline

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6-4 Sequential Circuit Analysis D A = AX + BX, D B = A\'X, Y = (A+B) X\' (input conditions for F-F) (conditions for yield Y) Figure 6-17 Example of a Sequential Circuit

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6-4 Sequential Circuit Analysis State Table useful relationship between data sources, yields, & flip-tumble state comprise of 4 areas: exhibit state, contribution, next state, yield list every single conceivable blend of present state and contributions next state demonstrates conditions of F-F one time period later at time t+1 State table case Table 6-1 State Table for Circuit of Figure 6-17

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6-4 Sequential Circuit Analysis State relationship A(t+1) = D A = AX + BX; B(t+1) = D B = A\'X; Y = AX\' + BX\' Two-dimensional state Table 6-2 Two-Dimensional State Table for the Circuit in Figure 6-17

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6-4 Sequential Circuit Analysis Mealy model the yields rely on upon the data sources and the states Moore show yields depend just on the states (a 1-D section suffices) a Moore display circuit D A = A  X  Y, Z = A Figure 6-18 Logic Diagram and State Table for DA = A  X  Y

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6-4 Sequential Circuit Analysis State Diagram The data (in a state table) might be spoken to graphically state by a circle & move between state by coordinated lines Figure 6-19 State Diagram # successive circuit of Fig 6-17 double number inside circle = condition of F-F coordinated lines are named with (information/yield) esteem # consecutive circuit of Fig 6-18 one F-F with 2 states, 2 inputs, no yield coordinated lines are named w/(input/yield) esteem

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6-4 Sequential Circuit Analysis Sequential Circuit Timing Figure 6-20 Sequential Circuit Timing Parameters

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6-4 Sequential Circuit Analysis Sequential Circuit Timing t p= t slack + ( t pd,FF + t pd,COMB + t s) t p ≥ max ( t pd,FF + t pd,COMB + t s) = t p ,min Figure 6-21 Sequential Circuit Timing Parths

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6-4 Sequential Circuit Analysis Ex6-1) Clock Period and Frequency Calculations 1.5ns= t slack + 0.2 +1.3 + 0.1 = t slack + 1.6ns Simulation Figure 6-22 Simulation Timing

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6-5 Sequential Circuit Design combinational circuit: completely determined by a truth table consecutive circuit requires a state table for its determination initial step is to get a state table (or state outline) No. of F-F is resolved from the no of states (up to 2 n ) Design Procedure 1) Obtain the state outline (from issue articulation, or state chart) 2) Obtain the state table 3) Assign double codes to the states 4) Derive F-F input conditions from next state conditions in table 5) Derive the yield capacities if necessary 6) Simplify the info conditions & yield capacities 7) Draw the rationale graph with D F-Fs & combinational doors

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6-5 Sequential Circuit Design Finding State Diagrams and State Tables Figure 6-23 Asynchronous and Synchronous Reset for D Flip-flops

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6-5 Sequential Circuit Design Finding State Diagram and State Tables Table6-3 State Table for State Diagram In Figure 6-21 Figure 6-24 Construction of a State Diagram for Example 6.2

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6-5 Sequential Circuit Design Ex6-3) Finding a State Diagram for a BCD-to-Excess-3 Decoder Table 6-4 Sequence Tables for Code Converter Example

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6-5 Sequential Circuit Design Figure 6-25 Construction of a State Diagram for Example 6.3

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6-5 Sequential Circuit Design Procedure 1) state outline 2) state table 3) F-F input conditions and yield capacities 4) Simplify the information conditions and yield capacities 5) rationale chart

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6-5 Sequential Circuit Design Sequence recognizer, 1101 Gray code 를 �� 당함 A, B, C, D: 00,01,11,10 Figure 6-24 Construction of a State Diagram for Example 6.2

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6-5 Sequential Circuit Design Designing with D Flip-Flops(ABX 로 truth table 작성 ) Table 6-5 Table 6-3 with Names Replaced by Binary Codes

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6-5 Sequential Circuit Design A(t+1) = DA(A,B,X) =  m(3,6,7) B(t+1) = DB(A,B,X) =  m(1,3,5,7) Y(A,B,X) =  m(5) Figure 6-26 Maps for Input Equations and Output Z

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6-5 Sequential Circuit Design Figure 6-27 Logic Diagram for Sequential Circuit with D Flip-Flops

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6-5 Sequential Circuit Design D Flip-Flops Designing with Unused States # A circuit with n F-F has 2n twofold states # unused states can be dealt with as couldn\'t care less conditions Table 6-6 State Table for Designing with Unused States

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6-5 Sequential Circuit Design D Flip-Flops Figure 6-28 Maps for Optimizing Input Equations

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6-5 Sequential Circuit Design D Flip-Flops Verification Figure 6-29 Test Sequence Generation for Simulation in Example 6.5

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6-5 Sequen

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