Check by means of Simulation .


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2. Check through Simulation. 3. Check by means of Simulation. Comprehensive simulationVery moderate (past slide)Environment modelingBlack box approachPartial simulationMay not get all errors1984, Pentium fdiv errorTest-vector generationSlow!Black box approach. 4. Confirmation by means of Simulation.
Transcripts
Slide 1

Co-reproduction Slides from: - Tony Givargis, Irvine, IC253 - Rabi Mahapatra, Texas A&M University - Sharif University

Slide 2

Abstraction Relative-speed Verification Time Real-time 1 hour FPGA 10 - 1 ~1 day Emulator 100 - 1 ~4 days Behavior (framework level) 1000 - 1 ~1.4 months Bus useful (framework level) 10000 - 1 ~1.2 years Cycle exact (framework level) 100000 - 1 ~12 years RTL 1000000 - 1 ~1 lifetime Gate-level 10000000 - 1 ~1 Millennium Verification by means of Simulation

Slide 3

Test-vector Generator System Under Test-seat Output Monitor Pass/come up short Verification by means of Simulation Exhaustive recreation Very moderate (past slide) Environment displaying Black box approach Partial reenactment May not get all blunders 1984, Pentium fdiv mistake Test-vector era Slow! Discovery approach

Slide 4

Stop/begin reproduction whenever Set information values Examine framework/environment values whenever Can venture through little interims (i.e., 500 nanoseconds) Simulation setup time (i.e., could invest more energy demonstrating environment than framework) Models likely inadequate Simulation speed much slower than real execution Verification by means of Simulation

Slide 5

Abstraction levels Event driven simulation:(gate level reenactment) Most exact as each dynamic flag is figured for each gadget amid the clock cycle as it spreads Each flag is recreated for its esteem and its season of event Excellent for timing investigation and confirm race conditions calculation escalated and thus moderate Cycle-based recreation: Calculate the condition of the signs at clock edge(0 or 1) reasonable for complex outline that requirements vast number of tests 10 times quicker than occasion driven reenactment, 20% region proficient

Slide 6

Abstraction levels Data-Flow Simulator Signals are spoken to as stream of qualities without thought of time. Useful squares are connected by signs. Squares are executed when signs exhibit at the information. Scheduler in the test system decides the request of piece executions. Abnormal state reflection reproduction utilized as a part of the early phases of confirmation, regularly to check the rightness of the calculations.

Slide 7

Overcoming Simulation Problems Reduce measure of continuous reenacted 1 msec execution rather than 1 hour 0.001sec * 10,000,000 = 10,000 sec = 3 hours Reduced certainty 1 msec of journey controller operation lets us know minimal Faster test system Emulators Special equipment for recreations Less exact/precise test systems Exchange speed for discernibleness/controllability

Slide 8

Overcoming Simulation Problems Don\'t require door level examination though reproductions Don\'t couldn\'t care less what happens at each information/yield of every rationale entryway Simulating RT segments ~10x speedier Cycle-based reproduction ~100x quicker Accurate at clock limits just No data on flag changes between limits Even speedier if utilizing direction set test systems Ideal for processors

Slide 9

HW/SW Co-Simulation Software is customarily completely tried after equipment is manufactured => long TTM Integrating HW and SW prior in the outline cycle => better TTM Co-reenactment includes Simulating a processor show alongside custom hw (normally portrayed in HDL)

Slide 10

High-level Co-recreation Functional (untimed) recreation permits one to: check utilitarian (halfway) rightness, by producing inputs and watching yields investigate the plan, by simple access to inward states High-level (planned) co-reenactment permits one to check: achievability investigation for particular equipment/programming parceling engineering choice (CPU, scheduler, ...) Cannot be utilized to approve the last usage require a significantly more nitty gritty model of HW and SW design

Slide 11

HW/SW Co-Simulation Variety of recreation methodologies exist From extremely point by point (e.g., door level model) To exceptionally extract (e.g., guideline level model) Simulation devices developed independently for equipment/programming Software: ordinarily with direction set test system (ISS) Hardware: commonly with models in HDL environment Integration of GPP/SPP on single IC making requirement for combining co-reproduction instruments

Slide 12

HW/SW Co-Simulation Simple/gullible way HDL model of chip runs framework programming HDL models of particular reason processors Integrate all models Hardware-programming co-test system ISS model of microchip runs framework programming HDL model of particular reason processors Create correspondence between test systems Simulators run independently aside from while exchanging information

Slide 13

HW/SW Co-Simulation Heterogeneous co-recreation situations (C-VHDL or C-Verilog) RPC or another type of between process correspondence amongst HW and SW test systems High overhead because of high information transmission between the test systems

Slide 14

Co-recreation techniques (contd) Heterogeneous co-reproduction Network distinctive kind of test systems together to accomplish better speed. Cases to be real co-recreation procedure as it manages better capacity to coordinate the errand with the apparatus, reproduces at the level of points of interest. Abstract\'s Eaglei: let hw keep running in numerous test systems, sw on local PC/workstation or in direction set-test system (ISS). Eaglie instrument interfaces all these. SW HW

Slide 15

Heterogeneous co-reproduction Homogenous/Heterogenous Product SW ISS (discretionary) Product SW figure Co-sim stick rationale HW Implementation VHDL Verilog Simulation calculation Event Cycle Dataflow Simulation Engine PC Emulator

Slide 16

Heterogeneous co-recreation How about execution? Sufficiently complex to portray any circumstance Since programming is not running at equipment reenactment speed, a superior execution will be acquired. On the off chance that objective CPU is not PC, you may utilize cross compiler When programming runs specifically on PC/WS, keeps running at the speed of WS When programming can not run straightforwardly as procedures on WS, you require guideline set test system ( ISS deciphers low level computing construct at direction level the length of CPU points of interest are not an issue) ISS more often than not keeps running at 20% of the speed of genuine or local procedures.

Slide 17

Hardware thickness of heterogeneous reproduction How much time programming gets to equipment? Equipment thickness relies on upon applications and with in an application. In inexactly coupled CPU framework, the square in charge of equipment introductions has 30% directions to get to the equipment. In firmly coupled framework, each memory reference could experience reenacted equipment. As a rule equipment thickness is essential for recreation speed. The base equipment and devices that impart between the heterogenous environment can add to the speed as well. On the off chance that reproduction is disseminated (it frequently happens nowadays), the system transmission capacity, dependability and speed matters as well

Slide 18

Emulation Special reenactment environment with equipment runs entire outline costly 10% of ongoing FPGA exhibits might be the equipment permit fashioners of vast items to discover a class of issue that can\'t be found in recreation can connect to genuine gadgets (switch utilizing Quickturn\'s Ethernet SpeedBridge could course genuine system activity)

Slide 19

Emulation Architectural test systems disregard equipment many-sided quality and need exactness Integration of HDL models with engineering level test system is quite ease back Best arrangement is to execute the Subsystem under Test in FPGA and incorporate this with the design level test system

Slide 20

Emulation - How it fits Simulator HDL Description Synthesize Emulation FPGA/ASIC Simulator

Slide 21

Strategy Simulation speed : Degrades when genuine parts supplant the practical pieces. The reenactment speed relies on upon recreation motor, the reproduction calculation, the quantity of doors in the plan, and whether the outline is principally synchronous or offbeat Low cost cycle based recreation is a decent trade off. Since it can not test physical normal for a plan, occasion driven test system might be utilized as a part of conjunction. Cycle based test systems and emulators may have long assemblage. Consequently, not reasonable for beginning tests that requirements many changes. Occasion driven and cycle based test systems have genuinely break even with troubleshooting situations, all signs are accessible at all circumstances. Emulators then again, require the rundown of signs to be followed to be announced at aggregation time

Slide 22

Strategy If the following issue can be found in a couple of microseconds of reenacted time, then slower test systems with speedier gathering times are suitable. On the off chance that the present clump of issues all take a few hundred milliseconds, or even seconds of recreated time, then the startup overhead of cycle based reproduction or even an emulator is justified regardless of the pick up in run time speed. What about the movability of test seats?

Slide 23

Processor Models Bus Functional Model (BFM) Instruction-Set Simulator (ISS)

Slide 24

Bus Functional Model (BFM) Encapsulates the transport usefulness of a processor Can execute transport exchanges on the processor transport (with cycle precision) Cannot execute any guidelines Hence, BFM is a unique model of processor that can be utilized to confirm how a processor collaborates with its peripherals

Slide 25

At early phases of the outline C/C++ BFM In the later phases of the plan ISS BFM Assembly SW HW Bus Functional Model (cont\'d)

Slide 26

Instruction-Set Simulator ISS: a processor show fit for mimicking execution of directions Different sorts of ISS for various purposes Usage 1: Verification of uses written in get together code For speediest speed: make an interpretation of target get together directions into host processor guidelines Is not cycle-exact. Extraordinarily for pipelined and superscalar structures

Slide 27

ISS (cont\'d) Different sorts of ISS … (cont\'d) Usage 2: Verification of timing and interface between framework parts Used in conjunction with a BFM ISS ought to time precise in this utilization ISS frequently fills in as an emulator For execution estimation use, ISS is to give exact cycle-tallying To have certain speed

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