CMOS VLSI Outline Address 1 3 : Configuration for Low Power.


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Expansion of compact shopper hardware. Worries on Environments and vitality ... Compact purchaser gadgets controlled by battery. Battery is overwhelming and ...
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CMOS VLSI Design Lecture 1 3 : Design for Low Power 11/27/2007, UTPA (embraced from Harris\' address notes)

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Outline Why low power plan? Force and Energy Dynamic Power Static Power Low Power Design 13: Design for Low Power

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Needs for Low Power VLSI Chips Power dissemination was dismissed because of Low gadget thickness Low working recurrence Now it is imperative issue because of High gadget thickness High working recurrence Proliferation of versatile customer hardware Concerns on Environments and vitality sources 13: Design for Low Power

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Moore\'s Law In 1965, Gordon Moore noticed that the quantity of transistors on a chip multiplied each 18 to 24 months. He made an expectation that semiconductor innovation will twofold its adequacy at regular intervals 13: Design for Low Power

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Moore\'s Law Electronics , April 19, 1965. 13: Design for Low Power

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Evolution in Complexity 13: Design for Low Power

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Transistor Counts 1 Billion Transistors K 1,000,000 100,000 Pentium ® III 10,000 Pentium ® II Pentium ® Pro 1,000 Pentium ® i486 i386 100 80286 8086 10 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected 13: Design for Low Power Courtesy, Intel

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Moore\'s law in Microprocessors 1000 2X development in 1.96 years! 100 10 P6 Pentium ® proc Transistors (MT) 486 1 386 0.1 286 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Transistors on Lead Microprocessors twofold like clockwork 13: Design for Low Power Courtesy, Intel

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Die Size Growth 100 P6 Pentium ® proc 486 Die size (mm) 10 386 286 8080 8086 ~7% development for every year 8085 8008 ~2X development in 10 years 4004 1 1970 1980 1990 2000 2010 Year Die size develops by 14% to fulfill Moore\'s Law 13: Design for Low Power Courtesy, Intel

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Frequency 10000 Doubles at regular intervals 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 386 10 8085 286 8086 8080 1 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors recurrence copies like clockwork 13: Design for Low Power Courtesy, Intel

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Power Dissipation 100 P6 Pentium ® proc 10 486 286 8086 Power (Watts) 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power keeps on expanding 13: Design for Low Power Courtesy, Intel

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Power will be a noteworthy issue 100000 18KW 5KW 10000 1.5KW 500W 1000 Pentium ® proc Power (Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power conveyance and scattering will be restrictive 13: Design for Low Power Courtesy, Intel

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Rocket Nozzle Nuclear Reactor Hot Plate Power thickness Sun Surface 10000 1000 Power Density (W/cm2) 100 8086 10 4004 P6 8008 Pentium ® proc 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power thickness too high to keep intersections at low temp 13: Design for Low Power Courtesy, Intel

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Small Signal RF Power RF Power Management 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Not Only Microprocessors Cell Phone Digital Cellular Market (Phones Shipped) (information from Texas Instruments) 13: Design for Low Power

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Battery Portable shopper hardware controlled by Battery is substantial and huge Energy thickness scarcely pairs in quite a long while Safety concern: the vitality thickness is drawing closer that of touchy chemicals. The battery innovation alone won\'t tackle the low power issue 13: Design for Low Power

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Reliability and Cooling Costs High power dispersal  high temperature  breakdown High execution microchips: ~50 Watts (a hand-held fastening iron) Packaging expense and cooling cost: fans Power supply rails: high transient current (e.g. 3A). 13: Design for Low Power

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Environmental Concerns Office robotization gear 5% of aggregate US business vitality in 1993 10% of aggregate US business vitality in 2000 Electricity era  air contamination and utilization of vitality sources 13: Design for Low Power

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Power and Energy Power is drawn from a voltage source joined to the V DD pin(s) of a chip. Quick Power: Energy: Average Power: 13: Design for Low Power

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Dynamic Power Dynamic force is required to charge and release load capacitances when transistors switch. One cycle includes a rising and falling yield. On rising yield, charge Q = CV DD is required On falling yield, charge is dumped to GND This rehashes Tf sw times over an interim of T 13: Design for Low Power

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Dynamic Power Cont. 13: Design for Low Power

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Dynamic Power Cont. 13: Design for Low Power

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Activity Factor Suppose the framework clock recurrence = f Let f sw = a f, where a = movement element If the sign is a clock, a = 1 If the sign switches once per cycle, a = ½ Dynamic entryways: Switch either 0 or 2 times for every cycle, a = ½ Static doors: Depends on outline, however regularly a = 0.1 Dynamic force: 13: Design for Low Power

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Short Circuit Current When transistors switch, both nMOS and pMOS systems might be quickly on the double Leads to a blip of "short out" current. < 10% of element force if rise/fall times are tantamount for information and yield 13: Design for Low Power

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Example 200 Mtransistor chip 20M rationale transistors Average width: 12 l 180M memory transistors Average width: 4 l 1.2 V 100 nm process C g = 2 fF/m 13: Design for Low Power

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Dynamic Example Static CMOS rationale entryways: action variable = 0.1 Memory clusters: action component = 0.05 (numerous banks!) Estimate dynamic force utilization per MHz. Disregard wire capacitance and short out current. 13: Design for Low Power

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Dynamic Example Static CMOS rationale doors: movement element = 0.1 Memory exhibits: action variable = 0.05 (numerous banks!) Estimate dynamic force utilization per MHz. Disregard wire capacitance. 13: Design for Low Power

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Static Power Static force is devoured notwithstanding when chip is peaceful. Ratioed circuits blaze power in battle between ON transistors Leakage draws power from ostensibly OFF gadgets 13: Design for Low Power

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Leakage Example The procedure has two edge voltages and two oxide thicknesses. Subthreshold spillage: 20 nA/m for low V t 0.02 nA/m for high V t Gate spillage: 3 nA/m for meager oxide 0.002 nA/m for thick oxide Memories utilize low-spillage transistors wherever Gates utilize low-spillage transistors on 80% of rationale 13: Design for Low Power

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Leakage Example Cont. Gauge static force: 13: Design for Low Power

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Leakage Example Cont. Gauge static force: High spillage: Low spillage: 13: Design for Low Power

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Leakage Example Cont. Gauge static force: High spillage: Low spillage: If no low spillage gadgets, P static = 749 mW (!) 13: Design for Low Power

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Low Power Design Reduce dynamic power a : C: V DD : f: Reduce static force 13: Design for Low Power

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Low Power Design Reduce dynamic power a : clock gating, rest mode C: V DD : f: Reduce static force 13: Design for Low Power

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Low Power Design Reduce dynamic power a : clock gating, rest mode C: little transistors (esp. on clock), short wires V DD : f: Reduce static force 13: Design for Low Power

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Low Power Design Reduce dynamic power a : clock gating, rest mode C: little transistors (esp. on clock), short wires V DD : least reasonable voltage f: Reduce static force 13: Design for Low Power

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Low Power Design Reduce dynamic power a : clock gating, rest mode C: little transistors (esp. on clock), short wires V DD : least reasonable voltage f: most reduced appropriate recurrence Reduce static force 13: Design for Low Power

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Low Power Design Reduce dynamic power a : clock gating, rest mode C: little transistors (esp. on clock), short wires V DD : most minimal reasonable voltage f: least appropriate recurrence Reduce static power Selectively utilize ratioed circuits Selectively utilize low V t gadgets Leakage diminishment: stacked gadgets, body predisposition, low temperature 13: Design for Low Power

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