Combinational Logic in Verilog .

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Verilog for Combinational CircuitsHow can Verilog be utilized to portray the different combinational building blocks?Can dependably utilize auxiliary styleThis can get dull
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Combinational Logic in Verilog

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Verilog for Combinational Circuits How can Verilog be utilized to depict the different combinational building pieces? Can simply utilize basic style This can get dull "Information stream" style is more advantageous relegate x = a & ~b (and so on, and so forth) Behavioral style is additionally great – we\'ll take a gander at this in the blink of an eye

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Verilog: 2x1 MUX Uses the restrictive ?: administrator Software fashioners loathe this administrator Hardware originators delight in its magnificence

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Verilog: 4x1 MUX (Data Flow Style) This is getting muddled! Require an approach to indicate a "gathering" of bits like w[0:3] Need an approach to supplant ?: with "if then else"

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Vectored Signals in Verilog Signals can be assembled as bit vectors The request of the bits is client decided W has 4 lines with the MSB = W[0] and the LSB = W[3] S has two lines with the MSB = S[1] and the LSB = S[0] Format is [MSB:LSB]

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s 0 s 1 w 0 w 3 s w 2 4 s 3 w 7 f w 8 w 11 w 12 w 15 Hierarchical Design of a 16x1 MUX Structural style Verilog The Verilog code for mux4x1 must be either in an indistinguishable record from mux16x1, or in a different document (called mux4x1.v) in an indistinguishable registry from mux16x1

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w y w y 0 w y w y 1 y 2 y En 3 y w y 4 0 w y 1 5 y 2 6 w y 2 En 0 3 7 w y 3 1 y 2 y w y w En 8 0 3 y w y 1 9 y 2 10 y En 3 11 y w y 12 0 w y 1 13 y 2 14 y En 3 15 Hierarchical Design of a 4 to 16 Decoder Structural style Verilog dec2to4 to be introduced soon … .

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Behavioral Style in Verilog Must be reg sort when utilized as LHS in a dependably piece Sensitivity list: proclamations inside the dependably square are just executed when at least one flags in the rundown changes esteem

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Always Blocks All LHS signals must be factors  sort reg The test system enrolls the esteem and keeps up it until the announcements in the dependably square are executed again Statements are re-executed just when a flag in the affectability list changes esteem The affectability list must incorporate all signs on which the LHS factors depend in the dependably square Order checks inside the dependably block!!!! In the event that … else is known as a procedural articulation All procedural proclamations must be inside a dependably piece

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Single versus Multiple Statements In Verilog, all develops allow just a solitary explanation If you require > 1 proclamation inside a build, utilize begin … … end This is like Pascal punctuation Verilog is for the most part more like C however You won\'t discover much use for start … end  most develops truly do incorporate only a solitary articulation

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Representation of Numbers can be given as constants in Binary (b) Octal (o) Hex (h) Decimal (d) For quantities of a predetermined size: TFAE: 12\'d2217 12\'h8A9 12\'o4251 12\'b100010101001 Numbers are 0-stretched out to one side, if essential, to round out the quantity of bits If the esteem surpasses the # of bits distributed, the additional bits are disregarded! #bits given in decimal

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4x1 MUX: Behavioral Styles

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More on Representation of Numbers Negative numbers: - 4\'b101  the 4 bit 2\'s supplement of 5  1011 For quantities of an unspecified size: TFAE: 2217 \'d2217 \'h8A9 \'o4251 \'b100010101001 The Verilog compiler picks the size to fit with alternate operands in the expression

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Case Statement Comparisons for a situation explanation are made a tiny bit at a time . No break articulation required – first match executes and after that case is left. Utilize start … end if > 1 proclamation required for a situation. If not all cases are counted, make a point to utilize default case.

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2 to 4 Decoder: Behavioral Style

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4 to 2 Binary Encoder Left reached out by x to fill 2 bits

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4 to 2 Priority Encoder casex versus case

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Case, Casez, Casex Case treats every esteem 0, 1, x, and z truly 4\'b01xz just matches 4\'b01xz Example: 4\'b0110 does not coordinate 4\'b01xx for a situation Casez treats 0, 1, and x truly Casez regards z as a couldn\'t care less Example: 4\'b0110 matches 4\'b01zz , yet not 4\'b01xz Casex treats 0 and 1 truly Casex regards both x and z as don\'t considerations Example: 4\'b0110 matches 4\'b01xx and furthermore 4\'b01xz No match here

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BCD to 7 Segment Display Converter

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For Loop When a circuit shows normality, a for circle can be utilized inside a dependably articulation to rearrange the plan portrayal (for circle is a procedural proclamation  just inside a dependably square ) C style grammar: for (k = 0; k < 4; k = k+1) Loop file must be sort whole number (not reg!) Can\'t utilize the accommodation of k++ Use start … end for various explanations tuned in Each emphasis of the circle indicates an alternate bit of the circuit Has nothing to do with changes over "time"

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2 to 4 Decoder Using a For Loop

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4 to 2 Priority Encoder Using a For Loop A flag that is relegated an esteem different circumstances in a dependably piece holds its last esteem  need conspire depends on this for right setting of Y and z

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Arithmetic Circuits

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Machine Arithmetic combinational circuits are required for Addition Subtraction Multiplication Division (equipment execution is discretionary) Addition/subtraction should be possible effortlessly utilizing full adders and at least extra rationale

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x y x y x y 1 0 n – 1 n – 1 c 1 c FA n - 1 n 0 2 s n – 1 0 MSB position LSB position Ripple-Carry Adder A swell convey viper falls full adders together Simple, however not the most effective outline Carry spread adders are more proficient

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Behavioral Style Full Adder We\'ve done full adders numerous ways as of now information stream styles behavioral style

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Behavioral Style Ripple-Carry Adder Allows a non specific size to be determined For n = 2, the for circle is proportional to: S[0] = X[0] ^ Y[0] ^C[0]; C[1] = (X[0] & Y[0]) | (X[0] & C[0]) | (Y[0] & C[0]); S[1] = X[1] ^ Y[1] ^C[1]; C[2] = (X[1] & Y[1]) | (X[1] & C[1]) | (Y[1] & C[1]);

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Higher Level Behavioral Style for Adder This won\'t work! Can\'t circle over "subcircuits" subcircuits to be instantiated like this are not permitted in a for circle

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Functions/Tasks Subcircuits can\'t specifically be instantiated in for circles Can\'t make a different module for fulladder and afterward instantiate that inside a for circle Need to make a capacity or an errand for the subcircuit Functions and undertakings give particular code without characterizing separate modules Defined inside a module Code is set in-line by the Verilog compiler Functions and errands are behavioral just

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Functions give measured code without characterizing separate modules Defined inside a module Can have many information sources (must have > 0), yet just a single yield Function is called like C++ capacities that have a non-void return esteem Functions can be brought in a persistent task or in a procedural articulation Functions contain just procedural explanations Function code is put in-line by the Verilog compiler

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More on Functions must have > 0 inputs Order of sources of info is managed by the request in which they are proclaimed in the capacity Functions can call different capacities, however not assignments May give back a vectored motion by pronouncing the capacity as: function [3:0] foo; //the range demonstrates a 4 bit result … endfunction

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Function Example: 16x1 MUX start … end required if more than 1 procedural proclamation in a capacity

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Tasks additionally give secluded code without characterizing separate modules Also characterized inside a module Can have many information sources and yields Task is called like C++ capacities that have a void return sort Outputs are returned through the yield factors (like the ports in a module) Task must be brought in a procedural explanation Tasks contain just procedural proclamations Task code is put in-line by the Verilog compiler

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More on Tasks may have any number of data sources and yields Order of information sources and yields is directed by the request in which they are announced in the assignment Tasks can call different assignments or capacities All contentions to an undertaking are verifiably of sort reg start … end square required in an errand in the event that you utilize > 1 procedural proclamation

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Ripple-Carry Adder Using a Task

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Generate Statement Verilog 2001 gives another announcement to instantiating separate modules inside a for circle Permits auxiliary style to use for circles create … endgenerate Use genvar datatype set up in whole number

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Ripple-Carry Adder Using Generate compiler produces n modules with names addstage[0].addbit, addstage[1].addbit, … , addstage[n-1].addbit

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y n – 1 0 ¤ Add Sub control x n – 1 0 c n - bit snake 0 n s n – 1 0 Subtractors Subtraction is the same as option X – Y = X + (- Y) where –Y is the 2\'s supplement of Y 2\'s supplement: - Y  (~Y) + 1 Complement all of Y and include 1 Another way is (Y  (11… 11)) + 1

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Macrofunctions Libraries of regular circuits, for example, adders, are accessible in most business CAD instruments Sometimes called macrofunctions or megafunctions Example: Quartus II gives a Library of Parametrized Modules (LPM) Each module is parametrized, e.g. the client can set the number bits utilized as a part of the module LPM_ADD_SUB is a n-bit viper/subtractor where you can pick the n it will utilize LPM_WIDTH Available in the "megafunctions math" library

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LPM_ADD_SUB Module add_sub = 1  dataa + datab + cin add_sub = 0  dataa - datab + (cin-1) Multi-bit signals must be named with [MSB..LSB]

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Sample Ap

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