Combinational Number-crunching Circuits.


45 views
Uploaded on:
Description
Half Adder. Including two single-piece parallel qualities, X, Y creates a whole S bit and a complete C-out piece. This operation is called half expansion and the circuit to acknowledge it is known as a half viper.. S(X,Y) = S (1,2)S = X\'Y XY\'S = X
Transcripts
Slide 1

Combinational Arithmetic Circuits Addition: Half Adder (HA). Full Adder (FA). Convey Ripple Adders. Convey Look-Ahead Adders. Subtraction: Half Subtractor. Full Subtractor. Obtain Ripple Subtractors. Subtraction utilizing adders. Augmentation: Combinational Array Multipliers.

Slide 2

X 0 1 Y 0 1 0 1 S 0 1 0 C-out 0 1 Half Adder Truth Table Outputs Inputs X Half Adder S C-OUT Y Half Adder Adding two single-piece twofold values, X, Y delivers a total S bit and a do C-out piece. This operation is called half expansion and the circuit to acknowledge it is known as a half snake. S(X,Y) = S (1,2) S = X\'Y + XY\' S = X Å Y C-out(x, y, C-in) = S (3) C-out = XY X Y Sum S C-out

Slide 3

X 0 1 Y 0 1 0 1 C-in 0 1 0 1 0 1 0 1 S 0 1 0 1 0 1 C-out 0 1 0 1 Sum S X XY 00 01 11 10 00 01 11 10 C-in C-in 1 6 0 2 4 0 1 0 1 3 5 7 1 C-in C-in Carry C-out Y 1 Full Adder Adding two single-piece parallel qualities, X, Y with a convey input bit C-in produces a total piece S and a do C-out piece. Full Adder Truth Table Outputs Inputs S = X\'Y\'(C-in) + XY\'(C-in)\' + XY\'(C-in)\' + XY(C-in) S = X Å Y Å (C-in) S(X,Y, C-in) = S (1,2,4,7) C-out(x, y, C-in) = S (3,5,6,7) C-out = XY + X(C-in) + Y(C-in)

Slide 4

X\' X\'Y\'C-in Y\' C-in X Y X Y X\' Sum S X\'YC-in\' X Y X\' Y\' Y C-in\' Full Adder C-out C-in X C-in Y C-in C-in\' C-in\' XY\'C-in\' X S Y XYC-in C-in\' X XY Y X XC-in C-out C-in Y YC-in C-in Full Adder Circuit Using AND-OR

Slide 5

X Y Sum S X Full Adder C-out C-in Y C-in S X XY Y X XC-in C-out C-in Y YC-in C-in Full Adder Circuit Using XOR

Slide 6

n-bit Carry Ripple Adders A n-bit snake used to include two n-bit paired numbers can worked by interfacing in arrangement n full adders. Every full viper speaks to a bit position j (from 0 to n-1). Every do C-out from a full viper at position j is associated with the convey in C-in of the full snake at the higher position j+1. The yield of a full viper at position j is given by: S j = X j Å Y j Å C j C j+1 = X j . Y j + X j . C j + Y . C j In the declaration of the aggregate C j must be produced by the full snake at the lower position j-1. The engendering delay in every full snake to create the convey is equivalent to two door delays = 2 D Since the era of the aggregate requires the proliferation of the convey from the least position to the most noteworthy position , the aggregate spread deferral of the viper is around: Total Propagation delay = 2 n D

Slide 7

Inputs to be included X3X2X1X0 Y3Y2Y1Y0 4-bit Adder C4 C0 =0 C-in C-out X0 Y0 X2 X1 X3 Y2 Y3 Y1 S3 S2 S1 S0 Full Adder Full Adder Full Adder Full Adder C3 C2 C1 Data contributions to be included C4 C0 =0 C-in C-in C-in C-in C-out C-out C-out C-out Sum Output S0 S1 S2 S3 Sum yield 4-bit Carry Ripple Adder Adds two 4-bit numbers: X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 delivering the entirety S = S3 S2 S1 S0 , C-out = C4 from the most critical position j=3 Total Propagation delay = 2 n D = 8 D or 8 entryway delays

Slide 8

Data contributions to be included X (X0 to X15) , Y (Y0-Y15) 4-bit Adder 4-bit Adder 4-bit Adder 4-bit Adder C12 C8 C4 C16 C0 =0 C-in C-in C-in C-in C-out C-out C-out C-out Sum yield S (S0 to S15) Y3Y2Y1Y 0 Y3Y2Y1Y 0 Y3Y2Y1Y 0 Y3Y2Y1Y 0 X3X2X1X0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 S3 S2 S1 S0 Larger Adders Example: 16-bit snake utilizing 4, 4-bit adders Adds two 16-bit inputs X (bits X0 to X15), Y (bits Y0 to Y15) delivering a 16-bit Sum S (bits S0 to S15) and a complete C16 from most huge position . Engendering delay for 16-bit viper = 4 x spread postponement of 4-bit snake = 4 x 2 n D = 4 x 8 D = 32 D or 32 door delays

Slide 9

Carry Look-Ahead Adders The impediment of the swell convey snake is that the proliferation deferral of snake (2 n D ) increments as the measure of the snake, n is expanded because of the help swell through all the full adders. Convey look-ahead adders utilize an alternate technique to make the required convey bits for every full viper with a lower consistent defer equivalent to three door delays. The complete C-out from the full viper at position i or C j+1 is given by: C-out = C i+1 = X i . Y i + (X i + Y i ) . C i By characterizing: G i = X i . Y i as the convey produce work for position i (one door delay) (If G i =1 C i+1 will be created paying little heed to the esteem C i ) P i = X i + Y i as the convey engender work for position i (one entryway delay) (If P i = 1 C i will be spread to C i+1 ) By utilizing the convey produce work G i and convey proliferate work P i , then C i+1 can be composed as: C-out = C i+1 = G i + P i . C i To take out convey swell the term C i is recursively extended and by increasing out, we acquire a 2-level AND-OR expression for every C i+1

Slide 10

Carry Look-Ahead Adders For a 4-bit convey look-ahead snake the extended expressions for all convey bits are given by: C 1 = G 0 + P 0 .C 0 C 2 = G 1 + P 1 .C 1 = G 1 + P1.G 0 + P 1 .P 0 .C 0 C 3 = G 2 + P 2 .G 1 + P 2 .P 1 .G 0 + P 2 .P 1 .P 0 .C 0 C 4 = G 3 + P 3 .G 2 + P 3 .P 2 .G 1 + P 3 . P 2 .P 1 .G 0 + P 3 .P 2 .P 1 .P 0 .C 0 where G i = X i . Y i P i = X i + Y i The extra circuits expected to understand the expressions are normally alluded to as the convey look-ahead rationale. Utilizing convey ahead rationale all convey bits are accessible after three entryway defers paying little heed to the measure of the viper.

Slide 11

Carry Look-Ahead Circuit C i = G i-1 + P i-1 . G i-2 + … . + P i-1 .P i-2 . … P 1 . G 0 + P i-1 .P i-2 . … P 0 . C 0

Slide 12

Binary Arithmetic Operations Subtraction Two twofold numbers are subtracted by subtracting every combine of bits together with getting, where required. Subtraction Example: 0 1 0 Borrow X 229 1 0 1 0 1 Y - 46 - 0 1 0 1 0 183 1 0 1 0 1

Slide 13

X 0 1 Y 0 1 0 1 D 0 1 0 B-out 0 1 0 Half Subtractor Truth Table Outputs Inputs X Half Subtractor D B-OUT Y Half Subtractor Subtracting a solitary piece twofold esteem Y from anther X (I.e. X - Y ) produces a distinction bit D and an obtain out piece B-out. This operation is called half subtraction and the circuit to acknowledge it is known as a half subtractor. D(X,Y) = S (1,2) D = X\'Y + XY\' D = X Å Y B-out(x, y, C-in) = S (1) B-out = X\'Y Difference D X Y B-out

Slide 14

X 0 1 Y 0 1 0 1 B-in 0 1 0 1 0 1 0 1 D 0 1 0 1 0 1 B-out 0 1 0 1 Difference D X XY 00 01 11 10 00 01 11 10 B-in B-in 1 6 0 2 4 0 1 0 1 3 5 7 1 B-in B-in Y Full Subtractor Subtracting two single-piece parallel qualities, Y, B-in from a solitary piece esteem X delivers a distinction bit D and a get out B-out piece. This is called full subtraction. Full Subtractor Truth Table Outputs Inputs S = X\'Y\'(B-in) + XY\'(B-in)\' + XY\'(B-in)\' + XY(B-in) S = X Å Y Å (C-in) Borrow B-out 1 S(X,Y, C-in) = S (1,2,4,7) C-out(x, y, C-in) = S (1,2,3,7) B-out = X\'Y + X\'(B-in) + Y(B-in)

Slide 15

X\' X\'Y\'B-in Y\' B-in Y X\' Difference D X\'YB-in\' X Y\' X\' Y B-in\' X B-in Y B-in B-in\' B-in\' XY\'B-in\' X Y XYB-in B-in\' X Y X\' X\'Y Y Full Subtractor B-out B-in X\' X\'B-in B-out B-in Y D YB-in B-in Full Subtractor Circuit Using AND-OR

Slide 16

X Y B-in X Y X\' X\'Y Y Full Subtractor B-out B-in X\' X\'B-in B-out B-in Y D YB-in B-in Full Subtractor Circuit Using XOR Difference D

Slide 17

n-bit Subtractors A n-bit subtracor used to subtract a n-bit number Y from another n-bit number X (i.e X-Y) can be inherent one of two courses: By utilizing n full subtractors and associating them in arrangement, making an obtain swell subtractor: Each get out B-out from a full subtractor at position j is associated with the get in B-in of the full subtracor at the higher position j+1. By utilizing a n-bit viper and n inverters: Find two\'s supplement of Y by: Inverting every one of the bits of Y utilizing the n inverters. Including 1 by setting the convey in of the minimum noteworthy position to 1 The first subtraction (X - Y) now turns into an expansion of X to two\'s supplement of Y utilizing the n-bit viper.

Slide 18

Inputs X3X2X1X0 Y3Y2Y1Y0 4-bit Subtractor B4 B0 =0 B-in B-out D3 D2 D1 D0 Difference Output D Data contributions to be subtracted X3 Y3 X2 Y2 X1 Y1 X0 Y0 B3 B2 B1 Full Subtractor Full Subtractor Full Subtractor Full Subtractor B4 B0 =0 B-in B-in B-in B-in B-out B-out B-out B-out D3 D2 D1 D0 Difference yield D 4-bit Borrow Ripple Subtractor Subtracts two 4-bit numbers: Y = Y3 Y2 Y1 Y0 from X = X3 X2 X1 X0 Y = Y3 Y2 Y1 Y0 creating the distinction D = D3 D2 D1 D0 , B-out = B4 from the most critical position j=3

Slide 19

4-bit Subtractor Using 4-bit Adder Inputs to be subtracted Y3 Y2 Y1 Y0 X3 X2 X1 X0 4-bit Adder C4 C0 = 1 C-out C-in S3 S2 S1 S0 D3 D2 D1 D0 Difference Output

Slide 20

Binary Multiplication is accomplished by including a rundown of moved multiplicands accordi

Recommended
View more...