Computerized Coordinated Circuits A Configuration Point of view.


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Prologue to advanced coordinated circuits. CMOS gadgets and assembling innovation. ... Advanced coordinated circuits have make some amazing progress and still have entirely ...
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Advanced Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Introduction July 30, 2002

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What is this book about? Prologue to advanced coordinated circuits. CMOS gadgets and assembling innovation. CMOS inverters and doors. Spread deferral, commotion edges, and power dispersal. Consecutive circuits. Number-crunching, interconnect, and recollections. Programmable rationale exhibits. Outline procedures. What will you realize? Understanding, outlining, and upgrading advanced circuits as for various quality measurements: cost, speed, power dispersal, and dependability

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Digital Integrated Circuits Introduction: Issues in computerized plan The CMOS inverter Combinational rationale structures Sequential rationale entryways Design techniques Interconnect: R, L and C Timing Arithmetic building pieces Memories and exhibit structures

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Introduction Why is planning advanced ICs distinctive today than it was some time recently? Will it change in future?

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The First Computer

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ENIAC - The main electronic PC (1946)

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The Transistor Revolution First transistor Bell Labs, 1948

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The First Integrated Circuits Bipolar rationale 1960\'s ECL 3-info Gate Motorola 1966

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Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation

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Intel Pentium (IV) microchip

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Moore\'s Law In 1965, Gordon Moore noticed that the quantity of transistors on a chip multiplied each 18 to 24 months. He made a forecast that semiconductor innovation will twofold its viability like clockwork

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Moore\'s Law Electronics , April 19, 1965.

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Evolution in Complexity

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Transistor Counts 1 Billion Transistors K 1,000,000 100,000 Pentium ® III 10,000 Pentium ® II Pentium ® Pro 1,000 Pentium ® i486 i386 100 80286 8086 10 Source: Intel 1 1975 1980 1985 1990 1995 2000 2005 2010 Projected Courtesy, Intel

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Moore\'s law in Microprocessors 1000 2X development in 1.96 years! 100 10 P6 Pentium ® proc Transistors (MT) 486 1 386 0.1 286 Transistors on Lead Microprocessors twofold like clockwork 8086 8085 0.01 8080 8008 4004 0.001 1970 1980 1990 2000 2010 Year Courtesy, Intel

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Die Size Growth 100 P6 Pentium ® proc 486 Die size (mm) 10 386 286 8080 8086 ~7% development for each year 8085 8008 ~2X development in 10 years 4004 1 1970 1980 1990 2000 2010 Year Die size develops by 14% to fulfill Moore\'s Law Courtesy, Intel

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Frequency 10000 Doubles at regular intervals 1000 P6 100 Pentium ® proc Frequency (Mhz) 486 386 10 8085 286 8086 8080 1 8008 4004 0.1 1970 1980 1990 2000 2010 Year Lead Microprocessors recurrence copies at regular intervals Courtesy, Intel

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Power Dissipation 100 P6 Pentium ® proc 10 486 286 8086 Power (Watts) 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Lead Microprocessors power keeps on expanding Courtesy, Intel

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Power will be a noteworthy issue 100000 18KW 5KW 10000 1.5KW 500W 1000 Pentium ® proc Power (Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 1971 1974 1978 1985 1992 2000 2004 2008 Year Power conveyance and dispersal will be restrictive Courtesy, Intel

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Rocket Nozzle Nuclear Reactor Hot Plate Power thickness 10000 1000 Power Density (W/cm2) 100 8086 10 4004 P6 8008 Pentium ® proc 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Power thickness too high to keep intersections at low temp Courtesy, Intel

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Small Signal RF Power RF Power Management 1996 1997 1998 1999 2000 Units 48M 86M 162M 260M 435M Analog Baseband Digital Baseband (DSP + MCU ) Not Only Microprocessors Cell Phone Digital Cellular Market (Phones Shipped) (information from Texas Instruments)

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Challenges in Digital Design µ DSM µ 1/DSM "Perceptible Issues" • Time-to-Market • Millions of Gates • High-Level Abstractions • Reuse & IP: Portability • Predictability • and so on … and There\'s a Lot of Them! "Tiny Problems" • Ultra-fast outline Interconnect • Noise, Crosstalk • Reliability, Manufacturability • Power Dissipation • Clock circulation. Everything Looks a Little Different ?

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(M) 10,000 100,000 10,000 1,000 100 1,000 10 100 Logic Transistor for every Chip 1 10 1 0.1 0.01 0.001 1981 1983 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 2005 2007 2009 Productivity Trends 10,000,000 100,000,000 Logic Tr./Chip 1,000,000 10,000,000 Tr./Staff Month. 100,000 1,000,000 58%/Yr. exacerbated Complexity 10,000 100,000 Productivity (K) Trans./Staff - Mo. Unpredictability development rate 1,000 10,000 x 100 1,000 21%/Yr. compound x Productivity development rate x 10 100 1 10 Source: Sematech Complexity outpaces plan profitability Courtesy, ITRS Roadmap

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Why Scaling? Innovation recoils by 0.7/era With each era can coordinate 2x more capacities for every chip; chip cost does not increment altogether Cost of a capacity diminishes by 2x But … How to outline chips with more capacities? Plan building populace does not twofold at regular intervals… Hence, a requirement for more effective outline strategies Exploit diverse levels of deliberation

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Design Abstraction Levels SYSTEM MODULE + GATE CIRCUIT DEVICE G D S n+

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Design Metrics How to assess execution of an advanced circuit (door, square, … )? Fetched Reliability Scalability Speed (delay, working recurrence) Power dissemination Energy to play out a capacity

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Cost of Integrated Circuits NRE (non-repetitive building) costs plan time and exertion, veil era one-time cost component Recurrent costs silicon handling, bundling, test relative to volume corresponding to chip range

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NRE Cost is Increasing

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Die Cost Single pass on Wafer Going up to 12" (30cm) From http://www.amd.com

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Cost per Transistor cost: ¢-per-transistor 1 Fabrication capital expense for every transistor (Moore\'s law) 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1994 1982 1985 1988 1991 1997 2000 2003 2006 2009 2012

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Yield

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Defects an is around 3

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Some Examples (1994)

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Reliability― Noise in Digital Integrated Circuits V ( t ) v DD i ( t ) Inductive coupling Capacitive coupling Power and ground clamor

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V(y) V f OH V(y)=V(x) Switching Threshold V M V OL V(x) V OL OH Nominal Voltage Levels DC Operation Voltage Transfer Characteristic VOH = f (VOL) VOL = f (VOH) VM = f (VM)

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V out Slope = - 1 V OH Slope = - 1 V OL V IL IH in Mapping amongst simple and computerized signals V " 1 " OH V IH Undefined Region V IL " 0 " V OL

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Definition of Noise Margins "1" V OH Noise edge high NM H V IH Undefined Region V NM Noise edge low L IL V OL "0" Gate Input Gate Output

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Noise Budget Allocates gross commotion edge to expected wellsprings of clamor Sources: supply clamor, cross talk, obstruction, balance Differentiate amongst settled and relative commotion sources

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Key Reliability Properties Absolute commotion edge qualities are tricky a skimming hub is more effectively exasperates than a hub driven by a low impedance (as far as voltage) Noise safety is the more imperative metric – the ability to smother clamor sources Key measurements: Noise exchange capacities, Output impedance of the driver and information impedance of the collector;

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Regenerative Property Regenerative Non-Regenerative

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v 0 1 2 3 4 5 6 Regenerative Property A chain of inverters Simulated reaction

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N Fan-out N Fan-in and Fan-out M Fan-in M

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R = ¥ i R = 0 o The Ideal Gate V out Fanout = ¥ NM H = NM L = V DD/2 g =  V in

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An Old-time Inverter 5.0 NM 4.0 L 3.0 (V) 2.0 out V M NM H 1.0 0.0 1.0 2.0 3.0 4.0 5.0 (V) in

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Delay Definitions

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T = 2 " t " N p Ring Oscillator

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R v out v C in A First-Order RC Network t p = ln (2) t = 0.69 RC Important model – matches deferral of inverter

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Power Dissipation Instantaneous force: p ( t ) = v ( t ) i ( t ) = V supply i ( t ) Peak power: P crest = V supply i top Average force:

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Energy and Energy-Delay Power-Delay Product (PDP) = E = Energy per operation = P av  t p Energy-Delay Product (EDP) = quality metric of door = E  t p

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A First-Order RC Network R v out v C L in

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Summary Digital incorporated circuits have made considerable progress and still have very some potential left for the coming decades Some intriguing difficulties ahead Getting an unmistakable viewpoint on the difficulties and potential arrangements is the reason for this book Understanding the configuration measurements that represent advanced outline is urgent Cost, dependability, pace, force and vitality scattering

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