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# Consecutive Circuits ProblemsI .

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Description
We wish to outline a synchronous consecutive circuit whose state chart is appeared in Figure. The kind of flip-failure to be utilize is J-K. . Two flip-failures are expected to speak to the four states and are assigned Q0Q1. The data variable is named x.. . . Excitation table for JK flip-flop. Excitation table of the circuit.
Transcripts
Slide 1

﻿Calculation = Logic + Control Sequential Circuits Problems(I) Chapter 2 Prof. Sin-Min Lee Department of Mathematics and Computer Science

Slide 16

We wish to plan a synchronous successive circuit whose state outline is appeared in Figure. The sort of flip-flounder to be utilize is J-K Two flip-failures are expected to speak to the four states and are assigned Q0Q1. The information variable is marked x.

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. Excitation table for JK flip-tumble Excitation table of the circuit

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The disentangled Boolean capacities for the combinational circuit can now be inferred

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How would we decide the combinatorial ciccuit? This circuit has three sources of info, I, R, and the current A. It has one yield, DA, which is the craved next A. So we draw a truth table, as some time recently. For accommodation I added the name Next A to the DA segment But this table is just reality table for the combinatorial circuit.

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A partition by-three counter which yields one 1 for each 3 1\'s viewed as info (not really in progression.) After yielding a 1, it begins checking all once again once more. 1. To assemble this, will require three states, relating to 0, 1, or 2 1\'s seen in this way.

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Designing with JK Flip-Flops The outline of a successive circuit with other than the D sort is confounded by the way that the flip-tumble input conditions for the circuit must be gotten in a roundabout way from the state table. At the point when D-sort flip-failures are utilized, the information conditions are gotten specifically from the following state. This is not the situation for JK and different sorts of flip-failures. So as to decide the information conditions for these flip-flops, it is important to determine an utilitarian relationship between the state table and the info conditions.

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Flip-Flop Excitation Tables A table that rundowns the required contributions for a given change of state is known as an excitation table. Case of an excitation table is demonstrated as follows:

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Flip-Flop Excitation Tables (cont) The excitation table show four unique sorts of flip-failures. Every table has a segment for the present state Q (t), a section for the following state Q (t + 1), and a segment for every flip-flounder contribution to show how the required move is accomplished. The image X in the table speaks to a couldn\'t care less condition, which implies that it doesn\'t make a difference whether the info is 0 or 1.

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Flip-Flop Excitation Tables (cont) The excitation table for the D flip-tumble demonstrates that the following state is constantly equivalent to the D input and is autonomous of the present state. This can be spoken to logarithmically: D = Q (t + 1)

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Design Procedure The plan methodology for successive circuits with JK flip-failures is the same as that for consecutive circuits with D flip-flops, aside from that the info conditions must be assessed from the present-state to next-state move got from the excitation table.

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Design Procedure (cont) The benefit of utilizing JK - sort flip-flops when planning consecutive circuits is that there are such a variety of couldn\'t care less passages shows that the combinational circuit for the information conditions is probably going to be less difficult, in light of the fact that couldn\'t care less minterms for the most part help in getting less difficult expressions.

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Design Procedure (cont) In request to play out the reproduction, a clock, and in addition the info signals R and X, is required. In doing the recreation of any consecutive circuit, adequate time must be given in the clock time frame to each of the accompanying: 1. Every single flip-tumble and contributions to change; 2. The impacts of these progressions to proliferate through the combinational rationale of the circuit to the flip-flounder inputs; and 3. The setup of the flip-flops for the following clock edge to happen.

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