Direct Conversion Receivers .


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Direct Conversion Receivers. Qui Luu Dec 2, 2009. Agenda. Wireless communication architectures Dual IF Superheterodyne, Low IF Sampling Single IF Superheterodyne, High IF Sampling Direct (Zero-IF) Conversion Homodyne receiver challenges DC offset Quadrature errors Even order distortions
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Slide 1

Coordinate Conversion Receivers Qui Luu Dec 2, 2009

Slide 2

Agenda Wireless correspondence structures Dual IF Superheterodyne, Low IF Sampling Single IF Superheterodyne, High IF Sampling Direct (Zero-IF) Conversion Homodyne recipient challenges DC balance Quadrature blunders Even request twists Origins of DC counterbalance LO bolster through Common mode bungle Theory behind quadrature mistakes Amplitude and stage jumble Consequences of DC and Quadrature blunder EVM Occupy accessible data transmission Implementation of DC and quadrature adjustment Results Summary

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Receive Architectures Dual IF Superheterodyne, Low IF Sampling Cos( ω LO - ω IF )Cos( ω LO )=Cos(2 ω LO - ω IF )+Cos( ω IF ) Cos( ω LO + ω IF )Cos( ω LO )=Cos(2 ω LO + ω IF )+Cos( ω IF )

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Receive Architectures Dual IF Superheterodyne, Low IF Sampling Large RF/IF content RF front end Fixed last LO recurrence and blender, reconfigurable first LO recurrence and possibly blender Final IF intensifier HD2/HD3 may require more keen hostile to nom de plume channel Distributed RF pick up facilitates per square clamor/pick up/IP exchange off Typically utilized for multi-band single bearer outlines IF extents to 15MHz

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Receive Architectures Single IF Superheterodyne, High IF Sampling Cos( ω LO - ω IF )Cos( ω LO )=Cos(2 ω LO - ω IF )+Cos( ω IF ) Cos( ω LO + ω IF )Cos( ω LO )=Cos(2 ω LO + ω IF )+Cos( ω IF )

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Receive Architectures Single IF Superheterodyne, High IF Sampling Cuts out one blender arrange Puts the last blender prerequisites on the ADC Last IF blend done in computerized space (advanced complex down blend) RF front end Band reconfigurable first LO recurrence and perhaps blender Final IF speaker HD2 for the most part of no worry Reduced RF pick up dispersion requires higher performing RF/IF ADC needs great IF execution (nyquist or under-example) IF ranges from 100-300MHz

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Receive Architectures Direct (Zero-IF) Conversion Phase and Gain Error LNA(t)= α 1 x(t)+ α 2 x 2 (t) input(t)=A 1 Cos( ω 1 t)+A 2 Cos( ω 2 t) feedthrough(t)= α 2 A 1 A 2 Cos( ω 2 - ω 1 )t Cos( ω RF ) Cos( ω RF )=1+Sin 2 ( ω RF ) Cos( ω SIG ) Cos( ω SIG )=1+Sin 2 ( ω SIG ) Phase and Gain Error

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Homodyne Receiver Advantages and Challenges Advantages: Low segment check prompts bring down framework cost No picture dismiss channel required Filtering necessities more casual at baseband Gain stages at baseband give control investment funds Challenges: DC balance showing up at baseband Self blending Offset voltages Images showing up symmetrically around zero recurrence I/Q befuddles in stage and plentifulness Even request nonlinearities Two high recurrence interferers near the channel of premium can bring about even request non-linearities that fall inside the band of premium.

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The Imperfect I/Q Demodulator Gain Imbalance (G1,G2,G3,G4) Imbalance In Phase Splitter Offset Voltages

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Imperfections in the I/Q Signal Path PCB and Layout bungles Offsets inside the double channel ADC Component jumbles

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Back to Basics : Euler\'s Formulas Sin  0 t is 90 out of stage concerning cos  0 t With flawless abundancy and stage coordinating the flag content at -  0 crosses out

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Amplitude and Phase Mismatch Amplitude Mismatch Phase Mismatch Desired Signal Image

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Effects of Gain, Offset, and Phase Errors

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What is bringing on the low quality of this demodulated Constellation? Exceptionally poor LO Quadrature Phase Split (in DMOD) DC Offset of the total heavenly body (presumably LO to RF Leakage) Noise has developed the impression of the group of stars focuses (poor Receiver Noise Figure) Symbol Decision Threshold If the image arrives on the edge or outside of the container, bit mistakes will happen

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Effects of I/Q Mismatch ** Images Occupy BW ** Interfere with Desired Signal ** Desired Signal Gain Error Phase Error Ideal ** EVM Degradation **

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DC Offset and Quadrature Error Correction DC balance and quadrature blunder remedy actualized digitally toward the end of the get chain Most productive approach so as to make up for all potential befuddles or mistakes in the flag way DC Correction If DC free coding is utilized, a step channel can be connected Quadrature Error Correction Gain Correction Calculate I^2 – Q^2 to decide the power contrast amongst I and Q. The power contrast ought to be headed to zero. Stage Correction Perform a cross-increase amongst I and Q. Can be seen as a Mixer. The DC expression is relative to the stage distinction amongst I and Q. By definition this ought to be zero on the off chance that they are impeccably orthogonal.

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AD9262: Direct Conversion RX Signal Chain Discrete flag chain focusing on Multi-Carrier base stations. WCDMA, CDMA2000, TDSCDMA, WiMax, LTE ADL5523: 400 MHz to 4 GHz Low Noise Amplifier ADL5382: 700 MHz to 4 GHz Quadrature Demodulator AD9262: 16-bit Dual Continuous Time Sigma-delta ADC Integrated DC and Quadrature Error Correction

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AD9269: Direct Conversion RX Signal Chain Discrete flag chain focusing on Multi-Carrier base stations. WCDMA, CDMA2000, TDSCDMA, WiMax, LTE ADL5523: 400 MHz to 4 GHz Low Noise Amplifier ADL5382: 700 MHz to 4 GHz Quadrature Demodulator AD9269: 16-bit Dual Pipeline ADC Integrated DC and Quadrature Error Correction

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CW Single Tone QEC Disabled DC Power: - 46.4 dB Image Rejection: 58.5 dB QEC Enabled DC Power: - 100 dB Image Rejection: 112 dB

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WCDMA Carrier with GSM Blocker GSM blocker 10 MHz far from WCDMA transporter At the recieving wire, blocker control: - 25 dBm and WCDMA bearer: - 50 dBm QEC Disabled DC Power: - 46.8 dB Image Rejection: 60.8 dB QEC Enabled DC Power: Image Rejection: 99.2 dB

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WCDMA Carrier with Modulated Blocker 10 MHz far from WCDMA transporter At the radio wire, blocker control: - 40 dBm and WCDMA transporter: - 60 dBm QEC Disabled DC Power: - 46.9 dB Image Rejection: 56.7 dB QEC Enabled DC Power: - 105 dB Image Rejection: 63.2 dB

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Summary Direct change or homodyne collectors have there claim merits and difficulties. Pick up, stage, and counterbalance mistakes are a couple of the difficulties that can be tended to with quadrature blunder revision calculations Gain, stage, and balance blunders cause debasements in recipient EVM and affectability Quadrature blunder adjustment will enhance EVM and affectability Direct change offers favorable circumstances in power, cost and execution over IF testing designs Quadrature blunder rectification empowers feasible direct transformation answers for large scale level basestations Analog Devices\' original of QEC is accessible incorporated into the accompanying items AD9262 – double 16b persistent time sigma delta ADC AD9269 – double 16b pipeline ADC

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AD9262 16-Bit, 2.5/5/10MHz, 30-160MSPS Dual Continuous Time Sigma Delta ADC KEY FEATURES SNR: 84.5 dBFS to 10 MHz input SFDR: 87 dBc to 10 MHz input Noise Figure: 15dB Power: 675 mW Sample rate converter: 30-160 MSPS Selectable data transmission: 5/10/20MHz complex Passive info arrange No ADC driver speaker Alias resistant No Anti-Alias Filter Integrated Funtions: Decimation channel and Sample Rate Conv. Quadrature Error and DC counterbalance redress PLL clock multiplier Low float voltage reference Serial Control Interface 1.8 V Analog supply

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AD9269 : 16-Bit, 20/40/65/80 MSPS 1.8V DUAL ADC KEY BENEFITS Total Power Dissipation = 125 mW/ch @80Msps Outstanding Performance SNR = 77 dBFs @ fIN = 40 MHz @ 80 MSPS ENOB of 12.4 @ fIN = 40 MHz @ 80 MSPS SFDR = 88 dBFs @ fIN = 40 MHz @ 80 MSPS Excellent Linearity DNL = ±0.7 LSB (Typical) INL = ±5.5 LSB (Typical) 1.8V or 3.3V CMOS yields 650 MHz Full Power Analog Bandwidth 1Vp-p to 2Vp-p Input Voltage Range Data Clock Output Provided User Controls by means of Serial port interface Output Data Format and Mux\'d Options Clock Duty Cycle Stabilizer Output Test designs Analog info go conformity Power down modes Quadrature Error Correction 16-bit and 14-bit Pin Compatible family AD9268-125 (16-bit), AD9258-125 (14-bit) AD9251 (14-bit), AD9231 (12-Bit), AD9204 (10-bit)

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