ECE 352 Computerized Framework Basics.


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The paired data put away in an advanced framework can be extensively ... Marked with state name and double code. Register exchange and sign enactments recorded ...
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ECE 352 Digital System Fundamentals Prof. Lipasti and Prof. Schulte Week 11

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Topics Control units Algorithmic state machines (ASMs) ASM outlines Binary augmentation Hardwired control Sequence register and decoder One flip-flop per state strategy Microprogrammed control

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Digital System Control The parallel data put away in an advanced framework can be extensively named either information or control data. Information preparing happens in the datapath, utilizing microoperations executed as register exchanges. The control data is utilized to coordinate the exercises of the datapath circuits to create the proposed results, in view of the control state and control inputs.

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Control Unit The control unit regulates the general circuit operation by producing signals that control the register exchange operations. The control unit can be intended for various sorts of frameworks Programmable frameworks A grouping of directions are put away in memory, and after that recovered and executed by the control unit. Nonprogrammable frameworks The grouping of operations is controlled by the control rationale and control inputs as it were.

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Algorithmic State Machines (ASMs) An ASM outline indicates both the state arrangement and preparing activities. The ASM graph contains basically the same data as a state outline for the successive circuit, furthermore speaks to the datapath operations that will happen as an aftereffect of control unit yields. The ASM outline is developed from state boxes, choice boxes, and contingent yield boxes, connected with coordinated lines.

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ASM Chart – State Box The state enclose speaks to a state the control succession. Single section and leave focuses. Marked with state name and paired code. Register exchange and flag actuations recorded inside will happen on every check beat while in that state.

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ASM Chart – Scalar Decision Box The scalar choice box speaks to the impact of control inputs. Single passage and two ways out (marked 0 and 1). The crate records a solitary data variable or a boolean articulation of simply info variables. The assessment of the condition figures out which way is to be taken.

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ASM Chart – Conditional Output Box The contingent yield box indicates register exchanges or flag actuations that are to occur after a predetermined condition. Must be put in a way on the yield of one or more choice boxes.

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ASM Chart – Vector Decision Box The vector choice box speaks to the impact of various control inputs in a solitary structure. Single passage, 2 n exits for n-component vector. Replaces a tree of scalar choice boxes.

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ASM Chart Timing State box signal initiations and register exchanges happen on each check while in that state, i.e. Moore model circuit. Contingent yield box register exchanges happen on the following clock after the condition is valid (i.e in the following state), yet just happen once. Restrictive yield box yields happen in the meantime as the inputs that brought about the condition to change, i.e. Coarse model.

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ASM Chart Exercises Prepare an ASM graph for Project 2 CTL module Frequency counter fclock = 1Mhz, mean 1ms BCD blend lock (4 numbers) Correct key beep Wrong key time-out (100 timekeepers)

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Binary Multiplication A consecutive approach is utilized to perform what might as well be called hand duplication. For every 1 in the multiplier, we include a left-moved form of the multiplicand. This permits us to utilize only one viper and a movement register to collect the outcome as an incomplete item.

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Binary Multiplication Hardware

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Binary Multiplication ASM Chart Assume that the multiplier and multiplicand are stacked before beginning. What number of states are required? Draw an ASM outline demonstrating: The required states. The choices that are made. The register exchanges that happen.

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Hardwired Control When actualizing a control unit, we can break the issue into two sections; the part that figure out what happens next. the part that creates the yields. We break the ASM outline into two sections to do this; A table demonstrating the yields as an element of state and inputs. A rearranged ASM demonstrating only the state grouping.

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Binary Multiplier Implementation What operations are required for the registers in the parallel multiplier? Recognize the registers and operations. Name the control flags that will flag those operations. Decide the expressions for those control signals as an element of state and inputs. Amend the ASM chart to demonstrate only the state sequencing data. Relegate parallel codes to the states.

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Hardwired Control Design Methodologies Sequential rationale plan process State table, state outline, and so on. Succession register and decoder Uses an arrangement register (counter) and decoder to shape signals demonstrating every state. One flip-flop per state otherwise known as one-hot controller One flip-lemon is utilized to speak to every state The present state is spoken to by a flip-flop with a 1, all other flip-failures are 0.

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Sequence Register and Decoder Use a n-bit grouping register for m states (m ≤ 2 n ). Utilize a n-to-2 n decoder to give m signals relating to the states. The control yields are gotten from the decoder signals and the inputs. The FF data mathematical statements are acquired from the state yields and inputs, improving the work required. Apply to the multiplier case…

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One Flip-Flop Per State Method In this strategy, a flip-failure is utilized for every state. The present state is characterized by the flip-slump that contains a 1. The rationale outline is normally extremely straightforward utilizing this technique – one point of interest of doing it along these lines. The change from ASM outline to equipment is immediate.

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One Flip-Flop Per State Method Alternatively, the data rationale to every flip-failure can be seen as giving a 1 if and just on the off chance that this flip-lemon is the present state and no state change will happen, or, this flip-lemon is the following state and a state change will happen. Apply to the multiplier illustration…

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Microprogrammed Control depends on paired qualities (words) put away in memory. Every word indicates one or more microinstructions . An arrangement of microinstructions is a microprogram . The control words are recovered from control memory by read operations. Control memory might be writable.

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Operation Sequencer Determines the following control location to peruse from. Can leave succession in light of inputs. Control inputs Datapath status Next-location information

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Operation ROM contains the microprogram. Control Data Register (CDR) is discretionary.

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Wrapping Up Do the perusing for one week from now! Reading material 9.1-9.8 Work on Project 2! Due Friday 12/9 in class

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CTL Module The CTL module gives the general force on reset for the other transmitter modules, and after that heaps information into the FIFO as it gets to be accessible. The FIFO utilizes the done info to demonstrate that it has stacked the information. Your control rationale must guarantee that the packed info information is just put away in the FIFO once for every time the dav information is set to 1 (for a given information word, dav may stay at 1 for more than a solitary clock cycle). You may accept that dav will be 0 for no less than one clock between info information words, and that the info information is substantial the length of dav is a 1. On the off chance that the FIFO can\'t store the approaching information before dav gets to be 0, the information is lost. Inputs • done (FIFO information stockpiling finish): This is set to 1 to demonstrate that the FIFO has stacked the information that was displayed to it. • dav (information accessible): When dav is 1, there is legitimate information accessible for transmission. Yields • rst_out (synchronous reset): This yield gives a force on reset to the reset of the circuit. It must be set to 1 at all times while reset is a 1, then remain a 1 for 2 clock periods after reset has gone to 0. • (store information in FIFO) : Indicates to the FIFO that there is legitimate information to be put away. This yield must go to 0 when the FIFO demonstrates it has put away the information (done is a 1) or the information is not legitimate (dav has gone to 0).

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One FF per State ASM

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One FF per State ASM

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