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# ECM585 Uncommon Points in PC Outline Address 2. Combinational Rationale Outline 1.

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At that point a PC helped outline (CAD) apparatus creates the enhanced entryways. ... created in 1984 by Gateway Design Automation. turned into an IEEE standard (1364) in 1995 ...
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﻿ECM585 Special Topics in Computer Design Lecture 2. Combinational Logic Design 1 Prof. Taeweon Suh Computer Science Education Korea University

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Introduction A rationale circuit is made out of: Inputs Outputs Functional determination Timing detail

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Circuits Nodes Inputs: A , B , C Outputs: Y , Z Internal: n1 Circuit components E1, E2, E3

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Types of Logic Circuits Combinational Logic Memoryless Outputs dictated by current estimations of inputs Sequential Logic Has memory Outputs controlled by past and current estimations of inputs

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Rules of Combinational Composition Every circuit component is itself combinational Every hub of the circuit is either assigned as a contribution to the circuit or interfaces with precisely one yield terminal of a circuit component The circuit contains no cyclic ways: each way through the circuit visits every circuit hub at most once Example:

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Boolean Equations Functional particular of yields regarding inputs Example: S = F( A , B , C in ) C out = F( A , B , C in )

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Terminology The Complement of a variable A will be An A variable or its supplement is called l iteral The AND of one or more literals is known as an item or implicant Example: AB, ABC, B OR of one or more literals is known as an entirety Example: A + B Order of operations NOT has the most elevated priority, trailed by AND, then OR Example: Y = A + BC

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Sum-of-Products (SOP) Form All Boolean conditions can be composed in SOP frame A minterm is an item (AND) of literals including the majority of the inputs to the capacity Each line in a truth table has a minterm that is TRUE for that column (and just that line ) The capacity is shaped by ORing the minterms for which the yield is TRUE Thus, a total (OR) of items (AND terms) Y = F( A , B , C ) = AB + AB

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Product-of-Sums (POS) Form All Boolean conditions can be composed in POS shape A maxterm is a whole (OR) of literals Each line in a truth table has a maxterm that is FALSE for that line (and just that line ) The capacity is framed by ANDing the maxterms for which the yield is FALSE Thus, an item (AND) of entireties (OR terms) Y = F( A , B , C ) = ( A + B) ( A + B)

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Boolean Equations Example You are heading off to the cafeteria for lunch You won\'t have lunch (E: eat) If it\'s not open (O: open) If they just serve corndogs (C: corndogs) Write a truth table for figuring out whether you will have lunch (E)

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SOP & POS Form SOP – total of-items POS – result of-aggregates Y = AB Y = ( A + B )( A + B )( A + B )

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When to Use SOP and POS? SOP delivers the most limited conditions when the yield is valid on just a couple lines of a truth table POS is less difficult when the yield is false on just a couple lines of a truth table

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HDL Hardware portrayal dialect (HDL): permits planner to determine rationale work as it were. At that point a PC helped outline (CAD) device creates the advanced entryways. Most business outlines assembled utilizing HDLs Two driving HDLs: Verilog created in 1984 by Gateway Design Automation turned into an IEEE standard (1364) in 1995 VHDL Developed in 1981 by the Department of Defense Became an IEEE standard (1076) in 1987

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HDL to Gates Simulation Input qualities are connected to the circuit Outputs checked for rightness Millions of dollars spared by investigating in recreation rather than equipment We are going to utilize ModelSim Xilinx Edition-III (MXE-III) for reproduction http://www.xilinx.com/ise/optional_prod/mxe.htm Synthesis Transforms HDL code into a netlist portraying the equipment (i.e., a rundown of entryways and the wires associating them) You can see the combined result with ISE Webpack IMPORTANT: When depicting circuits utilizing a HDL, it\'s basic to think about the equipment the code ought to deliver.

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Verilog Modules Two sorts of Modules: Behavioral: depict what a module does Structural: portray how a module is worked from more straightforward modules

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Behavioral Verilog Example Verilog: module example(input a, b, c, yield y); dole out y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule

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Behavioral Verilog Simulation Verilog: module example(input a, b, c, yield y); appoint y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule

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Behavioral Verilog Synthesis Verilog: module example(input a, b, c, yield y); dole out y = ~a & ~b & ~c | a & ~b & ~c | a & ~b & c; endmodule Synthesis:

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Verilog Syntax Verilog is case touchy. In this way, reset and Reset are not the same sign. Verilog does not permit you to begin sign or module names with numbers. Thus, for instance, 2mux is an invalid name. Verilog overlooks whitespace. Remarks come in single-line and multi-line assortments:/single line remark/* multiline remark */

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Structural Modeling - Hierarchy module and3(input a, b, c, yield y); appoint y = a & b & c; endmodule module inv(input a, yield y); relegate y = ~a; endmodule module nand3(input a, b, c yield y); wire out;/inward flag and3 andgate(a, b, c, out);/example of and3 inv inverter(out, y);/occasion of inverter endmodule

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Bitwise Operators module gates(input [3:0] a, b, yield [3:0] y1, y2, y3, y4, y5);/* Five distinctive two-information rationale doors following up on 4 bit transports */allot y1 = a & b;/AND allocate y2 = a | b;/OR dole out y3 = a ^ b;/XOR dole out y4 = ~(a & b);/NAND dole out y5 = ~(a | b);/NOR endmodule/single line remark/*… */multiline remark

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Reduction Operators module and8(input [7:0] a, yield y); dole out y = &a;/&a is much less demanding to compose than/dole out y = a[7] & a[6] & a[5] & a[4] &/a[3] & a[2] & a[1] & a[0]; endmodule

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Conditional Assignment module mux2(input [3:0] d0, d1, info s, yield [3:0] y); dole out y = s ? d1 : d0; endmodule ? : is likewise called a ternary administrator since it works on 3 inputs: s , d1 , and d0 .

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Internal Variables module fulladder(input a, b, cin, yield s, cout); wire p, g;/interior hubs dole out p = a ^ b; appoint g = a & b; dole out s = p ^ cin; allot cout = g | (p & cin); endmodule

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Precedence Order of operations Highest Lowest

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Numbers Format: N \'Bvalue N = number of bits, B = base N \'B is discretionary however suggested (default is decimal)

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Bit Manipulations: Example 1 allocate y = {a[2:1], {3{b[0]}}, a[0], 6\'b100_010};/if y is a 12-bit flag, the above articulation produces: y = a[2] a[1] b[0] a[0] 1 0 1 0/underscores (_) are utilized for arranging just to make it less demanding to peruse. Verilog disregards them.

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Bit Manipulations: Example 2 Verilog: module mux2_8(input [7:0] d0, d1, information s, yield [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]);/from slide 12 mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]);/from slide 12 endmodule Synthesis:

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Z: Floating Output Verilog: module tristate (info [3:0] an, info en, yield [3:0] y); allocate y = en ? a : 4\'bz; endmodule Synthesis:

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Delays module example(input a, b, c, yield y); wire abdominal muscle , bb, cb , n1, n2, n3; dole out #1 { stomach muscle , bb, cb } = ~{a, b, c}; dole out #2 n1 = abdominal muscle & bb & cb ; allot #2 n2 = a & bb & cb ; dole out #2 n3 = a & bb & c; dole out #4 y = n1 | n2 | n3; endmodule

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Delays module example(input a, b, c, yield y); wire abdominal muscle, bb, cb, n1, n2, n3; relegate #1 {ab, bb, cb} = ~{a, b, c}; allocate #2 n1 = abdominal muscle & bb & cb; dole out #2 n2 = a & bb & cb; dole out #2 n3 = a & bb & c; appoint #4 y = n1 | n2 | n3; endmodule

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Testbenches HDL code kept in touch with test another HDL module, the gadget under test (dut), additionally called the unit under test (uut) Not synthesizeable Types of testbenches: Simple testbench Self-checking testbench Self-checking testbench with testvectors (will be clarified later)

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Example Write Verilog code to actualize the accompanying capacity in equipment: y = bc + abdominal muscle Name the module sillyfunction

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Example Write Verilog code to execute the accompanying capacity in equipment: y = bc + stomach muscle Name the module sillyfunction Verilog: module sillyfunction(input a, b, c, yield y); dole out y = ~b & ~c | a & ~b; endmodule

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Simple Testbench module testbench1(); reg a, b, c; wire y;/instantiate gadget under test sillyfunction dut (a, b, c, y);/apply inputs each one in turn beginning start a = 0; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; a = 1; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; end endmodule

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Self-checking Testbench module testbench2(); reg a, b, c; wire y;/instantiate gadget under test sillyfunction dut(a, b, c, y);/apply inputs each one in turn/checking results introductory start a = 0; b = 0; c = 0; #10; if (y !== 1) \$display("000 failed."); c = 1; #10; if (y !== 0) \$display("001 failed."); b = 1; c = 0; #10; if (y !== 0) \$display("010 failed."); c = 1; #10; if (y !== 0) \$display("011 failed.");

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Self-checking Testbench (cont.) a = 1; b = 0; c = 0; #10; if (y !== 1) \$display("100 failed."); c = 1; #10; if (y !== 1) \$displ

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