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EE534 VLSI Design System Summer 2004 Lecture 7: Static Dynamic CMOS inverter CHAPTER 6 .

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Category: General / Misc
Description
Computation of Delay times: Average current strategy . . . The normal current amid high to low move can be figured by utilizing the present qualities toward the starting and the end of the move.. . The normal current amid low to high move can be computed by utilizing the present qualities toward the starting and the end of the move..
Transcripts
Slide 1

﻿EE534 VLSI Design System Summer 2004 Lecture 7: Static Dynamic CMOS inverter (CHAPTER 6)

Slide 2

Calculation of Delay times: Average current technique The normal current amid high to low move can be ascertained by utilizing the present qualities toward the start and the finish of the move. The normal current amid low to high move can be ascertained by utilizing the present qualities toward the start and the finish of the move.

Slide 3

Review: Inverter delay, falling Total fall delay = (t 1 - t 0 ) + (t 2 - t 1 )

Slide 4

Review: Inverter delay, rising Similar figuring with respect to falling postpone Separate into districts where PMOS is in straight, immersion

Slide 5

Review: CMOS inverter real defer What if input has limited ascent/fall time? not a stage beat Both transistors are on for some measure of time Capacitor charge/release current is decreased Empirical conditions:

Slide 6

Review: Propagation defer recreation comes about At short channel width, the deferral approaches a farthest point estimation of around 0.2nsec , which is for the most part dictated by innovation particular parameters, autonomous of outward capacitance segment.

Slide 7

Review: Inverter delay returned to (Lower V dd Increases Delay)

Slide 8

CMOS Ring Oscillator Circuit

Slide 9

CMOS Ring Oscillator Circuit (cont.) T=  PHL1 +  PLH1 +  PHL2 +  PLH2 +  PHL3 +  PLH3 =2  P + 2  P + 2  P =6  P

Slide 10

Calculation of interconnect postponement: Switch-level model (RC defer display) Model transistors as switches and resistances Resistance R on = normal resistance for a move For NMOS t phl : R P A R n C L A

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Switch-level model Delay estimation utilizing switch-level model (for general RC circuit): R n C L

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Propagation deferral of basic lumped RC arrange For fall postpone t phl , V 0 =V cc , V 1 =V cc/2 Standard RC-postpone conditions

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Interconnect delay – Elmore Delay For long interconnect lines, RC must be conveyed to get exact reenactment comes about Elmore Delay – first request time consistent basic, close guess of deferral

Slide 14

Interconnect Resistance is relative to cross-sectional zone As interconnect scales, increment viewpoint proportion to keep up same range.

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Review: Designing Inverters for Performance Reduce C L inward dissemination capacitance of the door itself interconnect capacitance fanout Increase W/L proportion of the transistor the most capable and compelling execution advancement instrument in the hands of the architect Increase V DD just negligible change in execution at the cost of expanded vitality dispersal Slope building - keeping signal ascent and fall times littler than or equivalent to the entryway engendering delays and of around equivalent values useful for execution useful for power utilization

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CMOS inverter Power Dissipation

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Why stress over power? - Power Dissipation Lead microchips control keeps on expanding 100 P6 Pentium ® 10 486 286 8086 Power (Watts) 386 8085 1 8080 8008 4004 0.1 1971 1974 1978 1985 1992 2000 Year Power conveyance and scattering will be restrictive Source: Borkar, De Intel 

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10000 1000 Rocket Sun\'s … chips may get to be distinctly hot… Nozzle Surface 100 Nuclear Power Density (W/cm2) Reactor 8086 10 4004 P6 Hot Plate 8008 Pentium ® 8085 386 286 486 8080 1 1970 1980 1990 2000 2010 Year Why stress over power? - Chip Power Density Source: Borkar, De Intel 

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On-Die Temperature Chip Power Density Distribution Power Map Power thickness is not consistently circulated over the chip Silicon is not a decent warmth conductor Max intersection temperature is dictated by problem areas Impact on bundling, w.r.t. cooling

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CMOS inverter control Power has three parts Static power : when info isn\'t exchanging Dynamic capacitive power : because of charging and releasing of load capacitance Dynamic short out power : guide current from V DD to G nd when both transistors are on

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CMOS inverter static power Static power utilization : Static current: in CMOS there is no static present the length of V in < V TN or V in > V DD +V TP Leakage current : dictated by "off" transistor Influenced by transistor width, supply voltage, transistor edge voltages V DD V DD I leak,p V DD V I <V TN Vo(low) Vcc I leak,n

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Drain intersection spillage Sub-limit current Gate spillage Leakage (Static) Power Consumption V DD I spillage Vout Sub-edge current is the predominant element. All expansion exponentially with temperature!

Slide 24

Leakage as a Function of V T Continued scaling of supply voltage and the consequent scaling of edge voltage will make subthreshold conduction a command segment of force dispersal. 10 - 2 A 90mV/decade V T move off - so each 255mV increment in V T gives 3 requests of size diminishment in spillage (yet unfavorably influences execution) 10 - 7 10 - 12

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Exponential Increase in Leakage Currents I spillage (nA/ m) Temp(C) From De,1999

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Dynamic Power Consumption Vdd Vin Vout C L

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Dynamic Capacitive Power and vitality put away in the PMOS gadget Case I: When the info is at rationale 0 : Under this condition the PMOS is directing and NMOS is in cutoff mode and the heap capacitor must be charged through the PMOS gadget. Control dispersal in the PMOS transistor is given by, P =i L V SD = i L (V DD - V O ) The current and yield voltages are connected by, i L =C L dv O/dt Similarly the vitality dissemination in the PMOS gadget can be composed as the yield changes from low to high , Above condition demonstrated the vitality put away in the capacitor C L when the yield is high.

Slide 28

Power Dissipation and Total Energy Stored in the CMOS Device Case II: when the information is high and out put is low: During exchanging all the vitality put away in the heap capacitor is dispersed in the NMOS gadget in light of the fact that NMOS is leading and PMOS is in cutoff mode. The vitality disseminated in the NMOS inverter can be composed as, The aggregate vitality scattered amid one exchanging cycle is, The power dispersed as far as recurrence can be composed as This inferred the power dissemination in the CMOS inverter is specifically corresponding to exchanging recurrence and V DD 2

Slide 29

Dynamic capacitive power Formula for element control: Observations Does not (straightforwardly) rely on upon gadget sizes Does not rely on upon changing postpone Applies to general CMOS entryway in which: Switched capacitances are lumped into C L Output swings from Gnd to V DD Input flag approximated as step capacity Gate switches with recurrence f Not an element of transistor sizes! Information subordinate - an element of exchanging action !

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Capacitance: Function of fan-out, wire length, transistor sizes Supply Voltage: Has been dropping with progressive eras Clock recurrence: Increasing… Lowering Dynamic Power P dyn = C L V DD 2 f

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Short Circuit Power Consumption Vin I sc Vout C L Finite incline of the info flag causes an immediate current way between V DD and GND for a brief timeframe amid exchanging when both the NMOS and PMOS transistors are leading.

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Dynamic short out power Short-circuit current streams from V DD to Gnd when both transistors are on Plot on VTC bend: I max : relies on upon immersion current of gadgets V CC I maximize V I D V in V CC

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Dynamic short out power Approximate short out present as a triangular wave Energy for every cycle: I max

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Short Circuit Currents Determinates Duration and slant of the info flag, t sc I top controlled by the immersion current of the P and N transistors which rely on upon their sizes , prepare innovation, temperature, and so on solid capacity of the proportion amongst information and yield inclines a component of C L P sc = t sc V DD I top f 0 1

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I sc  0 I sc  I max Impact of C L on P sc Vin Vout Vin Vout C L C L Large capacitive load Output fall time fundamentally bigger than info rise time. Little capacitive load Output fall time considerably littler than the information rise time.

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I crest as a Function of C L x 10 - 4 When stack capacitance is little, I pinnacle is huge. C L = 20 fF C L = 100 fF I crest (A) Short circuit dissemination is limited by coordinating the ascent/fall times of the information and yield signals - slant building . C L = 500 fF x 10 - 10 time (sec) 500 psec input incline

Slide 37

P sc as a Function of Rise/Fall Times When stack capacitance is little (t sin/t sout > 2 for V DD > 2V) the power is commanded by P sc V DD = 3.3 V P standardized V DD = 2.5 V If V DD < V Tn + |V Tp | then P sc is killed since both gadgets are never on in the meantime. V DD = 1.5V t sin/t sout W/L p = 1.125 m/0.25 m W/L n = 0.375 m/0.25 m C L = 30 fF standardized wrt zero information rise-time dispersal

Slide 38

Inverter control utilization Total power utilization

Slide 39

Power decrease Reducing dynamic capacitive power : Lower the voltage (Vdd) ! Quadratic impact on element control Reduce capacitance Short interconnect lengths Drive little door stack (little entryways, little fan-out) Reduce recurrence Lower clock recurrence - Lower flag action

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Power diminishment Reducing dynamic capacitive power : Lower the voltage (Vdd) ! Quadratic impact on element control Reduce capacitance Short interconnect lengths Drive little entryway stack (little doors, little fan-out) Reduce recurrence Lower clock recurrence - Lower flag movement

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Power diminishment Reducing dynamic capacitive power : Lower the voltage (V DD ) Quadratic impact on element control Reduce capacitance Short interconnect lengths Drive little door stack (little doors, little fan-out) Reduce recurrence Lower clock recurrence - Lower flag action

Slide 42

Examples f=500MHz C L =15fF/entryway V DD =2.5V P dyn

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