EECS 150 - Components and Design Techniques for Digital Systems Lec 02 CMOS Technology 9-2-04 .

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EECS 150 - Parts and Plan Strategies for Advanced Frameworks Lec 02
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EECS 150 - Components and Design Techniques for Digital Systems Lec 02 – CMOS Technology 9-2-04 David Culler Electrical Engineering and Computer Sciences University of California, Berkeley

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Outline Summary of last time Overview of Physical Implementations CMOS gadgets Announcements/Break CMOS transistor circuits fundamental rationale doors tri-state cradles flip-flops flip-slump timing nuts and bolts illustration utilize circuits

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We will learn in CS 150 … Language of rationale plan Logic advancement, state, timing, CAD devices Concept of state in computerized frameworks Analogous to factors and program counters in programming frameworks Hardware framework building Datapath + control = advanced frameworks Hardware framework plan philosophy Hardware depiction dialects: Verilog Tools to reenact plan conduct: yield = work ( inputs ) Logic compilers blend equipment squares of our outlines Mapping onto programmable equipment (code era) Contrast with programming outline Both guide details to physical gadgets Both must be immaculate… the value we pay for utilizing discrete math

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What is rationale outline? What is outline? Given issue spec, explain it with accessible parts While meeting criteria for size, cost, control, magnificence, polish, and so on. What is rationale plan? Pick advanced rationale parts to perform determined control, information control, or correspondence work and their interconnection Which rationale segments to pick? Numerous usage advancements (settled capacity parts, programmable gadgets , singular transistors on a chip, and so forth.) Design enhanced/changed to meet plan limitations

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What is computerized equipment? Gadgets that sense/control wires conveying advanced qualities (physical amount translated as "0" or "1") Digital rationale: voltage < 0.8v is "0", > 2.0v is "1" Pair of wires where "0"/"1" recognized by which has higher voltage (differential) Magnetic introduction means "0" or "1" Primitive computerized equipment gadgets Logic calculation gadgets (sense and drive) two wires both "1" - make another be "1" (AND) no less than one of two wires "1" - make another be "1" (OR) a wire "1" - then make another be "0" (NOT) Memory gadgets (store) store an esteem review an esteem beforehand put away sense drive AND sense Source: Microsoft Encarta

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Overview of Physical Implementations The stuff out of which we make frameworks. Incorporated Circuits (ICs) Combinational rationale circuits, memory components, simple interfaces. Printed Circuits (PC) sheets substrate for ICs and interconnection, conveyance of CLK, Vdd, and GND signals, warm dispersal. Control Supplies Converts line AC voltage to managed DC low voltage levels. Frame (rack, card case, ...) holds sheets, control supply, gives physical interface to client or different frameworks. Connectors and Cables.

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Primarily Crystalline Silicon 1mm - 25mm on a side 100 - 200M transistors (25 - 50M "rationale gates") 3 - 10 conductive layers 2002 - highlight measure ~ 0.13um = 0.13 x 10 - 6 m "CMOS" most normal - correlative metal oxide semiconductor Chip in Package Integrated Circuits Package gives: spreading of chip-level flag ways to board-level warmth dispersal. Clay or plastic with gold wires.

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Multichip Modules (MCMs) Multiple chips straightforwardly associated with a substrate. (silicon, fired, plastic, fiberglass) without chip bundles. Printed Circuit Boards fiberglass or earthenware 1-20 conductive layers 1-20in on a side IC bundles are patched down.

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Integrated Circuits Moore\'s Law has energized development throughout the previous 3 decades. "Number of transistors on a pass on duplicates at regular intervals." What are the symptoms of Moore\'s law?

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Integrated Circuits Uses for computerized IC innovation today: standard microchips utilized as a part of desktop PCs, and installed applications straightforward framework outline (generally programming advancement) memory chips (DRAM, SRAM) application particular ICs (ASICs) specially crafted to match specific application can be streamlined for low-control, ease, elite high-plan cost/moderately low assembling cost field programmable rationale gadgets (FPGAs, CPLDs) tweaked to specific application after creation brief time to advertise moderately high part cost institutionalized low-thickness segments still produced for similarity with more seasoned framework plans

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Switches: fundamental component of physical executions Implementing a basic circuit (bolt indicates activity if wire changes to "1"): A Z close switch (if An is "1" or stated) and turn on light (Z) Z An open switch (if An is "0" or unasserted) and kill light (Z) Z  A

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Cross Section The entryway demonstrations like a capacitor. A high voltage on the door draws in control into the channel. On the off chance that a voltage exists between the source and deplete a present will stream. In its least complex estimate the gadget demonstrations like a switch. CMOS Devices MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Beat View nFET pFET

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What Complementary about CMOS? Reciprocal gadgets work in sets G S D S D n-channel open when voltage at G is low closes when: voltage(G) > voltage (S) +  p-channel shut when voltage at G is low opens when: voltage(G) < voltage (S) – 

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Transistor-level Logic Circuits (inv) Inverter (NOT entryway): Vdd Gnd what is the connection amongst in and out? Vdd in out 0 volts Gnd 3 volts

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in out T F T Logical Values Threshold Logical 1 (genuine) : V > Vdd –V th Logical 0 (false) : V < Vth Noise edge? +3 Logic 1 Logic 0 Input Voltage V out Logic 1 Input Voltage Logic 0 +5 V in not( out, in)

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Big thought: Self-reestablishing rationale CMOS rationale doors are self-reestablishing Even if the sources of info are defective, exchanging time is quick and yields go rail to rail Doesn\'t make any difference what number of you course Although proliferation defer builds Manage fan-out to guarantee sharp and finish move

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Element of Time Logical change is not prompt Broader advanced outline system needs to make it shows up in that capacity Clocking, postpone estimation, glitch shirking +3 Propagation postpone V out 0 +5 V in

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Announcements If you are on the hold up rundown and might want to get into the class you should: Turn in an interest for on third floor Soda Attend addresses and do the homework, the initial two weeks. In the second week of classes, go to the lab segment in which you wish to enlist. Give the TA your name and understudy ID. Afterward, we will handle the shortlist in light of these solicitations, and lab area openings.

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Announcements Reading task during the current week. Katz and Boriello, Chap 1 Chap 4 pp. 157-170 Homework 1 is posted - due week from friday

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Computing with Switches Compose switches into more perplexing (Boolean) capacities: B An AND Z  An and B An OR Z  An or B Two key structures: arrangement (AND) and parallel (OR)

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Inverter (NOT door): NAND entryway Logic Function: out = 0 iff both an AND b = 1 consequently out = (abdominal muscle)\' pFET system and nFET system are duals of each other. a b out 0 1 0 1 0 1 0 Transistor-level Logic Circuits - nand (out, a, b) How about AND entryway?

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nFET is utilized just to pass rationale zero. pFet is utilized just to pass rationale one. For instance, NAND door: Transistor-level Logic Circuits Simple lead for wiring up MOSFETs: Note: This administer is once in a while damaged by master planners under extraordinary conditions .

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NAND entryway NOR door Function: out = 0 iff both an OR b = 1 in this manner out = (a+b)\' Again pFET system and nFET system are duals of each other. Other more mind boggling capacities are conceivable. Ex: out = (a+bc)\' a b out 0 1 0 1 0 1 0 1 0 Transistor-level Logic Circuits - nor (out, a, b)

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Transistor circuit for transforming tri-state cradle: "high impedance" (yield disengaged) Transistor-level Logic Circuits Variations Tri-state Buffer Inverting cushion Inverted empower "transmission entryway" Tri-state supports are utilized when numerous circuits all interface with a typical transport. Just a single circuit at any given moment is permitted to drive the transport. All others "disengage".

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Transmission doors are the best approach to construct "switches" in CMOS. Both transistor sorts are required: nFET to pass zeros. pFET to pass ones. The transmission entryway is bi-directional (dissimilar to rationale doors and tri-state supports). Practically it is like the tri-state cradle, however does not associate with Vdd and GND, so should be consolidated with rationale doors or supports. Transmission Gate Is it self reestablishing?

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Multiplexor If s=1 then c=a else c=b Transistor Circuit for upsetting multiplexor: Transistor-level Logic Circuits - MUX

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Interactive Quiz Generate truth table for MUX Boolean expression? Can you manufacture an inverter out of a MUX? What about AND? mux (c, s, a, b) c all inclusiveness

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Combinational versus consecutive computerized circuits Simple model of an advanced framework is a unit with sources of info and yields: Combinational means "memory-less" advanced circuit is combinational if its yield values just rely on upon its data sources inputs yields framework

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Combinational rationale images Common combinational rationale frameworks have standard images called rationale entryways Buffer, NOT AND, NAND OR, NOR A Z A simple to actualize with CMOS transistors (the switches we have accessible and utilize most) Z B A Z B

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Sequential rationale Sequential frameworks Exhibit practices (yield values) that rely on upon present and in addition past information sources All genuine circuits are successive Outputs don\'t change momentarily after an info change Why

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