ELEC 5200-001/6200-001 PC Engineering and Outline Spring 2007 Memory Association (Section 7).


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Spring 07, Apr. 25, 27. ELEC 5200-001/6200-001 Lecture 13. 2. Sorts of Computer Memories. From the spread of:A. S. Tanenbaum, Structured Computer Organization, Fifth Edition, Upper SaddleRiver, New Jersey: Pearson Prentice Hall, 2006.. Spring 07, Apr. 25, 27. ELEC 5200-001/6200-001 Lecture 13. 3. Electronic Memory Devices.
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ELEC 5200-001/6200-001 Computer Architecture and Design Spring 2007 Memory Organization (Chapter 7) Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal vagrawal@eng.auburn.edu ELEC 5200-001/6200-001 Lecture 13

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Types of Computer Memories From the front of: A. S. Tanenbaum, Structured Computer Organization, Fifth Edition , Upper Saddle River, New Jersey: Pearson Prentice Hall, 2006. ELEC 5200-001/6200-001 Lecture 13

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Electronic Memory Devices ELEC 5200-001/6200-001 Lecture 13

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Random Access Memory (RAM) Address bits Address decoder Memory cell cluster Read/compose circuits Data bits ELEC 5200-001/6200-001 Lecture 13

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Static RAM (SRAM) Cell bit Word line Bit line Bit line ELEC 5200-001/6200-001 Lecture 13

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Dynamic RAM (DRAM) Cell Bit line Word line ELEC 5200-001/6200-001 Lecture 13

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Building a Computer with 1GHz Clock and 40GB Memory ELEC 5200-001/6200-001 Lecture 13

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Trying to Buy a Laptop Computer? (Two Years Ago) IBM ThinkPad X40 23717GU 1.20 GHz Low Voltage Intel® Pentium® M, 1MB L2 Cache ~$5 Microsoft® Windows® XP Professional 512 MB DRAM ~$100 40 GB Hard Drive ~$40 2.71 lbs, 12.1" XGA (1024x768) IBM Embedded Security Subsystem 2.0 Intel PRO/Wireless Network Connection 802.11b, Gigabit Ethernet Integrated illustrations Intel Extreme Graphics 2 No CD/DVD drive PROP, Fixed Bay Availability**: Within 2 weeks $2,149.00 IBM web price* $1,741.65 deal price* ELEC 5200-001/6200-001 Lecture 13

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2006/07 Choose a Lenovo 3000 V Series to modify & purchase Processor Intel Core 2 Duo T5500 (1.66GHz, 2MBL2, 667MHzFSB) Total memory 512MB PC2-5300DDR2 SDRAM Hard drive 80GB, 5400rpm Serial ATA Weight 4.0lbs ELEC 5200-001/6200-001 Lecture 13

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Cache Processor does all memory operations with reserve. Miss – If asked for word is not in reserve, a square of words containing the asked for word is conveyed to store, and after that the processor demand is finished. Hit – If the asked for word is in store, read or compose operation is performed straightforwardly in reserve, without getting to fundamental memory. Piece – least measure of information exchanged amongst store and primary memory. Processor words Cache little, quick memory pieces Main memory huge, economical (moderate) ELEC 5200-001/6200-001 Lecture 13

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Inventor of Cache M. V. Wilkes, "Slave Memories and Dynamic Storage Allocation," IEEE Transactions on Electronic Computers , vol. EC-14, no. 2, pp. 270-271, April 1965. ELEC 5200-001/6200-001 Lecture 13

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Cache Performance Average get to time = T1 × h + Tm × (1 – h) = Tm – (Tm – T1) × h where T1 = store get to time (little) Tm = memory get to time (substantial) h = hit rate (0 ≤ h ≤ 1) Hit rate is otherwise called hit proportion, miss rate = 1 – hit rate Processor Access time = T1 Cache Small, quick memory Access time = Tm Main memory vast, economical (moderate) ELEC 5200-001/6200-001 Lecture 13

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Average Access Time Acceptable miss rate < 10% Tm – (Tm – T1) × h Access time Desirable miss rate < 5% T1 miss rate, 1 – h 0 h = 1 h = 0 ELEC 5200-001/6200-001 Lecture 13

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Comparing Performance Processor with 1 cycle memory get to, CPI = 1 Assume memory get to time of 10 cycles Assume 30% directions require memory information get to Processor with reserve Assume hit rate 0.95 for guidelines, 0.90 for information Assume miss punishment (time to peruse memory into store and from it) is 17 cycles Comparing times of 100 guidelines: Time without reserve 100 ×10 + 30×10 ──────────── = ──────────────────────────── Time with cache 100(0.95×1+0.05×17) + 30(0.9×1+0.1×17) = 5.04 ELEC 5200-001/6200-001 Lecture 13

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Controlling Miss Rate Increase reserve measure More squares can be kept in store; shot of miss is lessened. Bigger store is slower. Increment piece measure More information accessible; decreased possibility of miss. Less pieces in store increment shot of miss. Bigger pieces require more opportunity to swap. Store Blocks Large memory Cache Blocks Large memory ELEC 5200-001/6200-001 Lecture 13

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Increasing Hit Rate Hit rate increments with reserve estimate. Hit rate gently relies on upon square size. 90% 95% 100% 10% Cache measure = 4KB Decreasing odds of getting divided information Decreasing odds of covering information region hit rate, h 5% miss rate = 1 – hit rate 16KB 64KB 0% 16B 32B 64B 128B 256B Block estimate ELEC 5200-001/6200-001 Lecture 13

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The Locality Principle A program tends to get to information that shape a physical group in the memory – numerous gets to might be made inside a similar square. Physical territories are worldly and may move over longer timeframes – information not utilized for quite a while is more averse to be utilized as a part without bounds. Upon miss, the slightest as of late utilized (LRU) square can be overwitten by another piece. P. J. Denning, "The Locality Principle," Communications of the ACM , vol. 48, no. 7, pp. 19-24, July 2005. ELEC 5200-001/6200-001 Lecture 13

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Data Locality, Cache, Blocks Memory Increase piece size to match region measure Increase reserve size to incorporate most information Cache Data required by a program Block 1 Block 2 ELEC 5200-001/6200-001 Lecture 13

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Types of Caches Direct-mapped store Partitions of size of store in the memory Each segment subdivided into squares Set-cooperative store ELEC 5200-001/6200-001 Lecture 13

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LRU Direct-Mapped Cache Memory Cache Swap-out Data required by a program Block 1 Block 2 Data required Swap-in ELEC 5200-001/6200-001 Lecture 13

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LRU Set-Associative Cache Memory Swap-out Cache Data required by a program Block 1 Swap-in Swap-in Block 2 Data required ELEC 5200-001/6200-001 Lecture 13

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Direct-Mapped Cache 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Cache of 8 squares file (residential area) estimate = 1 word tag 00 10 11 01 00 10 11 000 001 010 011 100 101 110 111 32 word-addressable memory store address: label file Main memory 11 101 → memory address ELEC 5200-001/6200-001 Lecture 13

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Direct-Mapped Cache 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Cache of 4 squares Block measure = 2 word record (residential location) 32 word-addressable memory 00 11 00 10 00 01 10 11 0 1 square counterbalance reserve address: label file square balance Main memory 11 10 1 → memory address ELEC 5200-001/6200-001 Lecture 13

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Number of Tag and Index Bits Cache Size = w words Main memory Size=W words Each word in reserve has one of a kind file (nearby addr.) Number of list bits = log 2 w Index bits are imparted to square balance when a piece contains a bigger number of words than 1 Assume parcels of w words each in the primary memory. W/w such segments, each recognized by a label Number of label bits = log 2 (W/w) ELEC 5200-001/6200-001 Lecture 13

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Direct-Mapped Cache (Byte Address) 00000 00 00001 00 00010 00 00011 00 00100 00 00101 00 00110 00 00111 00 01000 00 01001 00 01010 00 01011 00 01100 00 01101 00 01110 00 01111 00 10000 00 10001 00 10010 00 10011 00 10100 00 10101 00 10110 00 10111 00 11000 00 11001 00 11010 00 11011 00 11100 00 11101 00 11110 00 11111 00 Cache of 8 pieces Block estimate = 1 word list tag 00 10 11 01 00 10 11 000 001 010 011 100 101 110 111 32-word byte-addressable memory reserve address: label file Main memory 11 101 00 → memory address byte balance ELEC 5200-001/6200-001 Lecture 13

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b6 b5 b4 b3 b2 b1 b0 Finding a Word in Cache Memory address Tag 32 words byte-address byte counterbalance Index Valid 2-bit Index bit Tag Data 000 001 010 011 100 101 110 111 Cache measure 8 words Block estimate = 1 word = Data 1 = hit 0 = miss ELEC 5200-001/6200-001 Lecture 13

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How Many Bits Cache Has? Consider a fundamental memory: 32 words; byte address is 7 bits wide: b6 b5 b4 b3 b2 b1 b0 Each word is 32 bits wide Assume that store square size is 1 word (32 bits information) and it contains 8 pieces. Reserve requires, for every word: 2 bit label , and one substantial piece Total stockpiling required in store = #blocks in store × (information bits/square + label bits + legitimate piece) = 8 (32+2+1) = 280 bits ELEC 5200-001/6200-001 Lecture 13

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A More Realistic Cache Consider 4 GB, byte-addressable primary memory: 1Gwords; byte address is 32 bits wide: b31… b16 b15… b2 b1 b0 Each word is 32 bits wide Assume that store piece size is 1 word (32 bits information) and it contains 64 KB information , or 16K words, i.e., 16K squares. Number of reserve list bits = 14, in light of the fact that 16K = 2 14 Tag estimate = 32 – byte counterbalance – #index bits = 32 – 2 – 14 = 16 bits Cache requires, for every word: 16 bit label , and one substantial piece Total stockpiling required in reserve = #blocks in reserve × (information bits/square + label measure + legitimate bits) = 2 14 (32+16+1) = 16 ×2 10 ×49 = 784×2 10 bits = 784 Kb = 98 KB Physical capacity/Data stockpiling = 98/64 = 1.53 But, need to build the square size to coordinate the extent of region. ELEC 5200-001/6200-001 Lecture 13

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Cache Bits for 4-Word Block Consider 4 GB, byte-addressable fundamental memory: 1Gwords; byte address is 32 bits wide: b31… b16 b15… b2 b1 b0 Each word is 32 bits wide Assume that reserve square size is 4 words (128 bits information) and it contains 64 KB information , or 16K words, i.e., 4K pieces. Number of store file bits = 12, in light of the fact that 4K = 2 12 Tag estimate =

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