ESE370: Circuit-Level Demonstrating, Configuration, and Advancement for Computerized Frameworks.


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Penn ESE370 Fall 2010 - Townley (DeHon) Side perspective: R.R. Harrison, ECE 5720 notes (Utah) ... Recognize the full custom and standard cell areas on 386DX bite the dust ...
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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 12: October 4, 2010 Layout and Area

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Today Layout Transistors Gates Design rules Standard cells 2

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Transistor Side perspective 3

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Layout Sizing & situating of transistors Designer controls W,L t bull settled Sometimes thick/thin oxide "flavors" 4

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NMOS Geometry L W Top perspective 5

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NMOS Geometry Color plan Red: door Green: source and deplete zones (n sort) Where is t bull ? L S G D W Top perspective 6

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t bull Transistors worked by storing materials Constant rate of statement (nm/min) Time controls t bull Oxides crosswise over whole chip kept at same time Same interim So, thickness is consistent Process engineer sets quality to amplify: Yield Performance 7

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NMOS versus PMOS Mostly discussed NMOS so far PMOS: "inverse" in some sense NMOS based on p substrate, PMOS based on n substrate Name alludes to when channel is upset Rabaey content, Fig 2.1 8

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PMOS Geometry Color plan Red: entryway Orange: source and deplete territories (p sort) Green: n well NMOS based on p wafer Must add n material to construct PMOS L S G D W n well 9

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Body Contact "Fourth terminal" Needed to set voltage around gadget PMOS: V b = V dd NMOS: V b = GND At right: PMOS (orange) with body contact (dull green) Side perspective: R.R. Harrison, ECE 5720 notes (Utah) 10

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Interconnect How to interface transistors Different layers of metal Intermediate layers "Contact" - metal to transistor "By means of" - metal to metal Rabaey content, Fig 2.7k 11

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Interconnect Cross Section ITRS 2007 12

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Masks Define regions need to find in layer Think of "stencil" for material statement Use photoresist (PR) to frame the "stencil" Expose PR through cover PR breaks down in uncovered zone Material is stored Only "sticks" in zone w/broke down PR 13

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Masking Process Goal: draw a shape on the substrate Simplest illustration: draw a rectangle Mask Silicon wafer 14

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Masking Process First: store photoresist Silicon wafer Mask photoresist 15

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Masking Process Expose through veil UV light 16

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Masking Process Remove cover and create PR Exposed region disintegrates This is "sure photoresist" Negative photoresist? 17

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Masking Process Deposit metal through PR window Then break up outstanding PR Why not simply utilize veil? Veils are costly Shine light through cover to engraving PR Can reuse veil 18

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Logic Gates How to manufacture? Associate NMOS, PMOS utilizing metal HW4, section 6: figure out formats into entryways 19

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Inverter Layout Example 20

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Inverter Layout Example Start with PMOS, NMOS transistors Space for interconnect 21

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Inverter Layout Example 22

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Inverter Layout Example Add body contacts Connect doors of transistors 23

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Inverter Layout Example 24

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Inverter Layout Example Add contacts to source, channel, entryway, body Connect utilizing metal (blue) 25

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Design Rules Why not adjoining transistors? A lot of vacant space If region is cash, pack in however much as could reasonably be expected Recall: handling uncertain Margin of mistake for procedure variety 26

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Design Rules Contract between procedure engineer & fashioner Minimum width/dividing Can be (frequently are) procedure particular Lambda rules: adaptable configuration rules as far as  = 0.5 L min Can relocate outlines from comparative procedure Limited extension: 45nm procedure != 1 m 27

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2  2 3 1.5 6 contact Legend metal 1 n doping by means of entryway p doping metal 2 Design Rules: Some Examples 2

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Layout Revisited How to "decipher" circuit from format? 29

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Layout to Circuit 1. Recognize transistors 30 Penn ESE370 Fall2010 - DeHon

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Layout to Circuit 2. Include wires 31

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Layout to Circuit 2. Include wires 32 Penn ESE370 Fall 2010 - Townley (DeHon)

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Layout to Circuit 2. Include wires 33 Penn ESE370 Fall 2010 - Townley (DeHon)

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Layout to Circuit 2. Include wires 34 Penn ESE370 Fall 2010 - Townley (DeHon)

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Layout #2 (rehearse) 35

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Standard Cells Lay out entryways with the goal that statures match Rows of nearby cells Standardized sizes Motivation: robotized place and course EDA instruments change over HDL to design 36

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Standard Cell Area All cells uniform tallness inv nand3 Width of channel controlled by steering Cell range Identify the full custom and standard cell locales on 386DX bite the dust http://microscope.fsu.edu/chipshots/intel/386dxlarge.html

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Admin HW4 – slight upgrade online to illuminate Q1 HW3 – trickier than expected in spots Our estimate is 1, 2, possibly 7 (let us know whether that is not where) Office hours to clear up any outstanding disarray? Andre back for Wed. Address

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Big Idea Layouts are physical acknowledgment of circuit Geometry tradeoff Can diminish separating at the expense of yield Design principles Can go from circuit to format or design to circuit by review 39

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