Flex Circuit Plan for CCD Application.


58 views
Uploaded on:
Category: Home / Real Estate
Description
Points. Framework DescriptionCCD BackgroundFlex Circuit Design Constraints/IssuesThermal Analysis Signal respectability in view of transmission line reflectionsOptimized DesignConclusions. Framework Description. Effectively cooled CCD utilizing Thermoelectric CoolerOperating Temperature of - 100
Transcripts
Slide 1

Flex Circuit Design for CCD Application ECEN 5004 Jon Mah

Slide 2

Topics System Description CCD Background Flex Circuit Design Constraints/Issues Thermal Analysis Signal respectability in view of transmission line reflections Optimized Design Conclusions

Slide 3

System Description Actively cooled CCD utilizing Thermoelectric Cooler Operating Temperature of - 100 °C ± 0.1°C Serial Clock Speed of 1MHz CCD size is 4096 X 4096pixels 4 flex circuits Hermetic, emptied lodging (not envisioned) Concentrate on Base get together (dismissing outer preamps, and so on.)

Slide 4

Aside: CCD Background Starts with presenting the CCD to light. Charge works in potential wells by means of the photoelectric impact Step 1: V1=on, V2=off, V3=off

Slide 5

Moving Charge Using Clock Signals Step 2: V1=on, V2=on, V3=off Step 3: V1=off, V2=on, V3=off Step 5: V1=off, V2=off, V3=on Step 4: V1=off, V2=on, V3=on

Slide 6

Typical 4-Serial Readout For 4096 X 4096 dynamic territory, 2048 X 2048 readout every serial enroll (disregard overscan) So, for every parallel move, 2048 serial movements 1MHz is for serial (i.e. parallel is around 0.5KHz)

Slide 7

Serial Register Readout Pixels read out 1 at once Amplifiers, Reset Gate, Last Gates on Serial Register

Slide 8

CCD/Chip Carrier Specifications Split into 2 Si CCDs (2048 X 4096) Ceramic Chip Carrier 3 single parallel clock lines per flex circuit (12 lines) 3 single serial clock lines per flex circuit (12 lines) Last door, reset entryway and total well per flex circuit (12 lines) 8 input/yield predisposition lines per CCD (16 lines) 2 shields and 2 ground lines for every flex circuit (16 lines) Total of 68 flag lines 17 flag lines for every flex circuit

Slide 9

CCD/Chip Carrier Marconi Applied Technologies (Secrets of Marconi CCDs June 16-22, 2002)

Slide 10

Flex Circuits Deposited then scratched metal on adaptable (polyimide or polyester) substrate Three fundamental components: Base film Adhesive Conductor Microstrip transmission line Assume 12cm long Serial tickers, last entryway, reset entryway and aggregate well keep running at 1MHz and Parallel timekeepers keep running at 0.5KHz

Slide 11

Dielectric Films - Polyimide Material Properties CTE Thermal conductivity (k = 0.33W/mK) Relative Dielectric consistent ( ε r = 4.0) For an isothermal CCD we need: Matched CTE with the Adhesive and conduit (avoid delamination or breaking between interfaces) Low warm conductivity (keep up warm disconnection of CCD) Low electrical conductivity (Substrate ground plane unaffected by changes in the case)

Slide 12

Adhesive Material Properties CTE Dielectric steady Thermal conductivity (k = 0.23W/mK) For isothermal CCD outline, we need: Again, coordinated CTE with transmitters and dielectric film Low dielectric consistent to minimize capacitance Low warm conductivity to keep up isothermal CCD

Slide 13

Conductors - Copper Material properties CTE Good Electrical conductivity Thermal conductivity (390W/mK) For isothermal CCD plan, we need: Again, coordinated CTE to glue and base/cover movies Good electrical conductivity for lower inductance Low warm conductivity to keep up isothermal CCD

Slide 14

Design Considerations Wire securities from flex circuit security cushions to CCD security cushions are restricted to 25 μ m distance across gold wire with lengths of around 3mm (disregard for this investigation) CCD transporter has some warm resistance (disregard for this examination) Neglect convective warming/cooling impacts Geometry limits size of striplines to 2 μ m thickness Radiative warming is ~40mW Neglect warm produced in flex circuit because of force dispersal.

Slide 15

Thermal Performance of Stripline TEC can deal with up to 0.20W to keep up - 100 °C working temperature What are the warmth loads from the CCD to the flex circuit Dynamic Conduction Assume that the lodging is cleared (i.e. no convection) Assume a settled radiative warmth heap of 40mW 100˚C delta crosswise over flex (baseplate to CCD) Fixed glue thickness = 0.1 μ m

Slide 16

Thermoelectric Coolers Marlow MI4012T 4-organize TEC Assume that all the warmth is expelled from the baseplate Capable of dismissing 0.2W with Δ T = 100 ˚C Marlow Industries Inc.

Slide 17

Dynamic Heat Load Most of the warmth dispersed on the chip is because of the yield intensifier for every serial enroll Typical esteem is around 25mW for each enhancer, or 100mW aggregate

Slide 18

Thermal Conduction of Flex Circuits Fourier Equation Where k = Thermal Conductivity = 0.33W/mK for polyimide, 0.23W/mK for glue, and 390W/mK for Cu A = cross-sectional region = width x thickness Δ T = change in temp crosswise over flex circuit = 100K Δ x = separation of flex circuit = 12cm

Slide 20

Total Allowable Heat 100mW from element stacks This leaves 100mW for conduction and radiative warmth loads Assume 15mW for every flex circuit This confines the width of the conduits to around 450 μ m

Slide 21

Stripline Transmission Line Calculations Want to match trademark impedance to the Load 10Vp-p clock rails Function of conveyor width

Slide 22

Characteristic Impedance for a Microstrip Transmission Line Z 0 for a Microstrip w = width of transmitter d = stature of polyimide ε r = dielectric of polyimide Ramo, S., Whinnery, J., VanDuzer, T. Fields and Waves in Communications Electronics

Slide 24

Reflections Reflection coefficient is reliant on the heap and trademark impedances Changes definitely with conductor width How would we be able to change the heap resistance?

Slide 25

Sheet Resistance for Impedance Matching (Geometry)

Slide 26

Sheet Resistance for Impedance Matching (Doping fixation) Red – n-sort Blue – p-sort http://ece-www.colorado.edu/~bart/book/mobility.htm

Slide 28

Sine wave trustworthiness Reflection coefficient influences the flag respectability Design: 10Vp-p sine wave stack impedance of 10 Ω How ward is the flag to the conductor width? Resilience on creation of the conduit width is ~10%

Slide 30

Design Considerations Conductor width must be under 450 μ m Parallel and Serial timekeepers need distinctive load impedances since they have diverse frequencies Minimize affectability to reflections by moving the ρ = 0 indicate higher and right of the reflection coefficient bend This can be performed by changing doping and separations between bond cushions

Slide 33

Summary The warm plan compels the biggest channel width Impedance coordinating can be acquired by fluctuating the doping fixation and also separations of signs to grounds on the CCD The ideal outline for reflection is to have the biggest width, which then has the most astounding resistance to manufacture blunders Coupling, and different impacts (reflections because of flex circuits to bond cushions to wire bonds to bond cushions on the CCD) were disregarded in the examination

Recommended
View more...