IMAPS Worldwide Business Gathering Guide Process.

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IMAPS Global Business Council. Guide Process
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IMAPS Global Business Council Roadmap Process "The Road Ahead"

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The GBC Roadmap Team This Roadmap Process presentation was set up by these individuals from the IMAPS Global Business Council & National Technology Council: Steve Adamson ( Justin Blount ( Laurie Roth ( Lee Smith ( Andy Strandjord ( Jie Xue (

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Topics Where does IMAPS fit in with the ITRS and iNEMI Roadmaps? What is the ITRS Roadmap and how can it work? What is the iNEMI Roadmap and how can it work? How does IMAPS communicate with this Roadmap Process? Why IMAPS ought to be included. IMAPS Areas of Focus. In the event that you are now acquainted with the ITRS & iNEMI Roadmap Process, skip to slide 19 The Roadmaps: ITRS iNEMI Summary IMAPS Areas of Focus.

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ITRS & iNEMI Packaging Roadmaps Intersect iNEMI Market Requirements ITRS Tech Requirements Chip Level System Level IMAPS addresses the Semiconductor Packaging needs of this space.

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What is the ITRS? The International Technology Roadmap for Semiconductors (ITRS) is an appraisal of semiconductor innovation prerequisites. The target of the ITRS is to guarantee headways in the execution of coordinated circuits. This appraisal, called roadmapping, is a helpful exertion of worldwide industry producers and suppliers, government associations, consortia, and colleges. The ITRS recognizes the innovative difficulties and necessities confronting the semiconductor business throughout the following 15 years. It is supported by the European Semiconductor Industry Association (ESIA), the Japan Electronics and Information Technology Industries Association (JEITA), the Korean Semiconductor Industry Association (KSIA), the Semiconductor Industry Association (SIA), and Taiwan Semiconductor Industry Association (TSIA). SEMATECH is the worldwide correspondence place for this action. The ITRS group at SEMATECH likewise arranges the USA area occasions.

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ITRS Technology Working Groups The ITRS process empowers examination and open deliberation all through the group about the prerequisites for achievement. The key component in the achievement of the Roadmap is getting accord on industry drivers, prerequisites, and innovation courses of events . The Technology Working Groups are the associations that "build" the guides. These agents evaluate the condition of innovation and distinguish regions that may give arrangements. The TWG individuals additionally demonstrate open doors for new research and development. These gatherings are comprised of volunteer innovation specialists from chip fabricates, supplier organizations, colleges and the scholarly world, innovation labs, and semiconductor innovation consortia. The Technology Working Groups, otherwise called TWGs, are contained the specialized orders of System Drivers Design Test and Test Equipment Process Integration, Devices, and Structures RF and Analog/Mixed-signal Technologies for Wireless Communications Emerging Research Devices and Materials Front End Processes Lithography Interconnect Factory Integration Assembly and Packaging – This is the territory where IMAPS will center. Environment, Safety, and Health Yield Enhancement Metrology Modeling and Simulation .

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Example of ITRS Short Term Challenges

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iNEMI has solid industry support.

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iNEMI Roadmap Methodology iNEMI focusses on top level industry portions by means of their Product Emulator Groups. Moreover, they address innovation ranges by means of their diverse Technology Working Groups. A "cross-cut" lattice guarantees input between the different gatherings.

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iNEMI Technology Working Groups Business Processes/Technologies: Product Lifecycle Information Management Design Technologies: Environmentally Conscious Electronics Modeling, Simulation & Design Tools Thermal Management Manufacturing Technologies: Board Assembly Test, Inspection & Measurement Final Assembly Component Subsystem Technologies: Passive Components RF Components & Subsystems Packaging – This is one of the zones where IMAPS will center. Semiconductor Technology Organic Substrates Mass Data Storage Connectors Energy Storage Systems Optoelectronics Sensors Organic and Printed Electronics Ceramic Substrates – IMAPS likewise adds to this TWG .

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iNEMI Cross-cut Matrix A "cross-cut" network guarantees criticism between the different gatherings.

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Example of iNEMI fleeting difficulties

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Update timetable for ITRS/iNEMI 2006 ITRS Roadmap discharge booked for December 4, 2006. 2007 iNEMI Roadmap discharge planned for February 2007 at APEX, Los Angeles.

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Why IMAPS ought to be included. ITRS concentrates fundamentally on "front end" wafer fab territories, with a part on Semiconductor Assembly & Packaging. iNEMI concentrates fundamentally on "board level" get together, with a part on Semiconductor Assembly & Packaging. ITRS/iNEMI are cooperating to adjust their Semiconductor Assembly & Packaging Roadmaps. A large portion of the same individuals are on both groups. Some IMAPS individuals are likewise on both groups. IMAPS\' center is on Semiconductor Assembly & Packaging. It\'s a characteristic fit to take the yield of the ITRS/iNEMI Semiconductor Assembly & Packaging Roadmaps and utilize that yield to coordinate IMAPS\' exercises towards comprehending crevices in the guide. IMAPS\' corporate individuals will advantage by growing genuine industry answers for genuine industry challenges.

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Global Semiconductor Packaging Materials Outlook Market Size for Materials = Market Opportunities for IMAPS individuals. Source: SEMI Industry Research and Statistics and TechSearch International, November 2005 This estimate was supplied affability of SEMI & Techsearch International. The full report is accessible from SEMI\'s web inventory at .

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Launched "The Road Ahead" in Advancing Microelectronics 4/06

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Roll-out arrangement for IMAPS to address guides Form a GBC Roadmap Team.- DONE GBC Roadmap Team makes a guide format ("red block") and recognizes current holes on the current guides. - DONE GBC Roadmap Team imparts those holes to the NTC. GBC and NTC structure future IMAPS occasions to concentrate on those holes – continuous. Dave Saums to give short presentation at LED & Thermal ATWs in September 2006. Interim, GBC/NTC to bolster ITRS/iNEMI redesigns with information & convey back to IMAPS issues/patterns. Use IMAPS individuals on the ITRS/iNEMI guide TWGs to encourage correspondence: Laurie Roth, Howard Imhof....and different volunteers.

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Recommended Areas of Focus for IMAPS Members Develop Feasible Embedded Components . Create Enhanced Materials to Enable Wafer Level Packaging . Convey Solutions to Resolve Thermal Management Issues. Grow New Materials to Reduce System Cost While Delivering the Necessary Performance. Close the Gap Between Chip and Substrate Interconnect Density. Resolve the issues low K and Cu convey to Packaging.

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The Roadmaps

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The complete section can be downloaded from the ITRS site: The accompanying slides contain key portions.

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ITRS 2005 Semiconductor Packaging Roadmap Table of Contents All of these subjects – and those on the following slide – are extensively secured in the ITRS Roadmap. This presentation will concentrate on the key difficulties as it were. Bundling Materials Requirements New Materials Embedded and Integrated Passives Assembly and Packaging Infrastructure Challenges Electrical Design Requirements Cross Talk Power Distribution and Power Subsystem Thermo-mechanical Challenges in Electronic Packaging Mechanical Challenges Mechanical Modeling and Simulation and Validation Thermal Modeling and Simulation and Validation Equipment Requirements for Emerging Package Types Potential Solutions Wafer Level Packaging Chip to Next Level Interconnect Package to Board Interconnect Fine Pitch Ball Grid Array/CSP Packages Socketed Parts Embedded and Integrated Passives Package Substrates Build-Up and Coreless Substrates Rigid Substrate Technology Chapter Scope Difficult Challenges Technology Requirements Single Chip Packages High Pin-Count Packages Wafer Level Packaging System in a Package (Multi-chip Packages, 3D Packaging) Flexible Substrates and Interconnect Optoelectronic Packaging RF Packaging MEMS Medical and Bio Chip Packaging Biocompatibility Bio Packaging Reliability Integrated Circuit Manufacturing Cost Reliability Package and Interconnect Characterization and Simulation Reliability Testing Soft Errors

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ITRS 2005 Semiconductor Packaging Roadmap Table of Contents proceeded with System in Package (SiP) – System Level Integration Types/Categories of SiP\'s Side by Side Placement (Horizontal Packages) Stacked Structures Package-on-Package (POP), Package-in-Package (PiP) Stacked Die Packages Chip to Chip/Wafer Structure Embedded Structures Technologies for SiP Wafer level SiP and 3 D Integration Technologies for Embedded Devices Challenges for SiP Thermal administration System in Package Outlook Wafer Thinning Glossary of Terms Cross-Cut ITWG Issues Design Factory Integration Die Traceability Crosscut with Factory Integration Interconnect RF/AMS Wireless Environment, Safety and Health Modeling and Simulation Metrology Test

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ITRS: Single Chip Package Incremental changes in conventional gathering advancements won\'t be adequate to meet business sector necessities. The substrate commands the expense of single chip bundling. Taken a toll for each pin has been drifting up, rather than down. Working temperatures are an issue in cruel situations. Higher recurrence chip-to-board speeds for fringe transports.

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ITRS: High Pin-Count Packages Package pin check grows a

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