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# L27:Lower Power Algorithm for Multimedia Systems .

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Description
Substance. Algorithmic Effects on Low PowerLow Power ManagementLow Power ApplicationsLow Power Video ProcessorSingle Chip Video CameraVector QuantizationData EncodingCDMA Searcher Viterbi Decoder. Low Power Algorithm . Calculation Selection. Sample: 8x8 lattice DCT . Quality Reduction: DIGLOG multiplier.
Transcripts
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﻿L27:Lower Power Algorithm for Multimedia Systems 1999. 8 성균관대학교 조 준 동 http://vada.skku.ac.kr

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Contents Algorithmic Effects on Low Power Low Power Management Low Power Applications Low Power Video Processor Single Chip Video Camera Vector Quantization Data Encoding CDMA Searcher Viterbi Decoder

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Low Power Algorithm

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Algorithm Selection Example: 8x8 lattice DCT

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Strength Reduction: DIGLOG multiplier first Iter second Iter third Iter Worst-case mistake - 25% - 6% - 1.6% Prob. of Error<1% 10% 70% 99.8% With a 8 by 8 multiplier, the correct outcome can be acquired at a greatest of seven emphasis steps (thinking pessimistically)

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Logarithmic Number System - > Significant Strength Reduction

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Switching Activity Reduction (an) Average action in a multiplier as an element of the consistent esteem (b) A parallel and serial executions of a snake tree.

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System administration, System dividing, Algorithm determination Precompute physical capacitance of Interconnect and exchanging movement (number of transport gets to) Regularity: to limit the power in the control equipment and the interconnection organize. Seclusion: to endeavor information region through disseminated handling units, recollections and control. Spatial area: a calculation can be divided into normal bunches in view of availability Temporal locality:average lifetimes of factors (less fleeting stockpiling, likelihood of future gets to referenced in the current past). Few memory references: since references to recollections are costly as far as power. Framework Level Solutions

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System-Level Solutions - cont. Test system: Instruction-level Energy Estimation Software: Energy Efficient Algorithms OS: Voltage Scheduling Algorithms OS: Multiprocessing for Energy Microprocessor: Dynamic Caches

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Processor Systems:high Power Thinkpad (Pentium) ® 0.3 Hours/AA InfoPad (ARM) ® 0.8 Hours/AA Toshiba Portable (486) ® 0.9 Hours/AA Newton (ARM) ® 2.0 Hours/AA Operations per Battery Life: Minimize Energy Consumed per Operation Operations every Second: Maximize Throughput º Operations/second

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DPM (Dynamic Power Management): stops the clock exchanging of a particular unit produced by clock generators. SPM (Static Power Management): When the framework stays sit without moving for a huge period time, then it is closed down. DPM versus SPM Identify control hungry modules and search for chances to decrease control

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V dd versus Delay Use Variable Voltage Scaling or Scheduling for Real-time Processing Use design enhancement to make up for slower operation, e.g., Parallel Processing and Pipelining for simultaneous expanding and basic way lessening. Downsize gadget sizes to make up for deferral (Interconnects don\'t scale proportionately and can get to be distinctly predominant)

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Power PC 603 Strategy Baseline: utilize right supply and right recurrence to each piece of the framework If one needs to attend to the occurence of some information, just a little circuit could hold up and awaken the primary circuit when the info happens. PowerPC 603 is a 2-issue (2 guidelines read at once) with 5 parallel Execution units. 4 modes: Full on mode for full speed Doze mode in which the execution units are not running Nap mode which additionally stops the transport timing and the Sleep mode which stops the clock generator Sleep mode which stops the clock generator with or without the PLL (20-100mW).

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Power PC 603 Power Management

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TI Structures Two DSPs: TMS320C541, TMS320C542 diminish power and chip tally and framework cost for remote correspondence applications C54X DSPs, 2.7V, 5V, Low-Power Enhanced Architecture DSP (LEAD) family: Three diverse shut down modes, these gadgets are appropriate for remote interchanges items, for example, computerized mobile phones, individual advanced partners, and remote modem,low control on voice coding and unraveling The TMS320LC548 highlights: 15-ns (66 MIPS) or 20-ns (50 MIPS) direction process durations 3.0-and 3.3-V operation 32K 16-bit expressions of RAM and 2K 16-bit expressions of boot ROM on-chip Integrated Viterbi quickening agent that lessens Viterbi butterfly refresh in four guideline cycles for GSM channel translating Powerful single-cycle guidelines (double operand, parallel directions, contingent directions)

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InfoPad Architecture, UC-Berkeley Internet Wireless Basestation "PadServer" Speech Recognizer Web Browser Transmit sound and crude bitmaps over the remote connection Example: Hand-held discourse empowered web-program Maintain state in the system, not on the Pad Perform all calculation in the system to limit customer vitality dissemination

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Main information stream dealt with by custom low-control ASICs Packet Header Frame-support refresh Control Statistics Reliability Debugging 10 MIPS μProcessor RX Packet Frame Buffer InfoPad Hardware Flexibility Embedded programming in charge of abnormal state works Only header sent to microchip Radio Entire bundle steered to devoted equipment Use equipment/programming joining to give vitality productive abnormal state usefulness

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Multimedia I/O Terminal.

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Multimedia I/O terminal

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Intercom InfoPad Evolution Total Power: ~7 W Where did the power go? Wasteful execution Energy-Efficient Processors Commercial DC/DC No nearby calculation? Business radios High-level framework configuration upgrades finish arrangement and drives new research

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Power-Down Techniques

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Low Power Memory

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