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# Number-crunching Circuits (Part I) Randy H. Katz College of California, Berkeley Fall 2005.

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Inspiration. Math circuits are brilliant samples of brush. rationale plan.
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﻿Number juggling Circuits (Part I) Randy H. Katz University of California, Berkeley Fall 2005

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Motivation Arithmetic circuits are fantastic cases of brush. rationale plan • Time versus Space Trade-offs Doing things quick requires more rationale and in this way more space Example: convey lookahead rationale • Arithmetic Logic Units Critical segment of processor datapath Inner-most "loop" of most PC guidelines

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Binary Number Representation Sign & Magnitude, Ones Complement, Twos Complement Binary Addition Full Adder Revisted ALU Design BCD Circuits Combinational Multiplier Circuit Design Case Study: 8 Bit Multiplier Sequential Multiplier Circuit Overview

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Representation of positive numbers same in many frameworks Major contrasts are in how negative numbers are spoken to Three noteworthy plans: sign and extent ones supplement twos supplement Assumptions: we\'ll accept a 4 bit machine word 16 distinct qualities can be spoken to roughly half are certain, half are negative Number Systems Representation of Negative Numbers

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Number Systems Sign and Magnitude Representation High request bit is sign: 0 = positive (or zero), 1 = negative Three low request bits is the greatness: 0 (000) through 7 (111) Number range for n bits = +/ - 2 - 1 Representations for 0 n-1

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Cumbersome expansion/subtraction Must contrast sizes with decide indication of result Number Systems Sign and Magnitude Ones Complement N is sure number, then N is its negative 1\'s supplement n 4 N = (2 - 1) - N 2 = 10000 - 1 = 00001 1111 - 7 = 0111 1000 Example: 1\'s supplement of 7 = - 7 in 1\'s comp. Alternate way strategy: basically register bit savvy supplement 0111 - > 1000

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Subtraction executed by expansion & 1\'s supplement Still two representations of 0! This causes a few issues Some complexities also Number Systems Ones Complement

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Only one representation for 0 One more negative number than positive Number Representations Twos Complement like 1\'s comp aside from moved one position clockwise

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Number Systems Twos Complement Numbers n N* = 2 - N 4 2 = 10000 7 = 0111 1001 = repr. of - 7 sub Example: Twos supplement of 7 4 Example: Twos supplement of - 7 2 = 10000 - 7 = 1001 0111 = repr. of 7 sub Shortcut strategy: Twos supplement = bitwise supplement + 1 0111 - > 1000 + 1 - > 1001 (representation of - 7) 1001 - > 0110 + 1 - > 0111 (representation of 7)

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Number Representations Addition and Subtraction of Numbers Sign and Magnitude 4 + 3 7 0100 0011 0111 - 4 + (- 3) - 7 1100 1011 1111 outcome sign piece is the same as the operands\' sign when signs contrast, operation is subtract, indication of result relies on upon indication of number with the bigger greatness 4 - 3 1 0100 1011 0001 - 4 + 3 - 1 1100 0011 1001

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Number Systems Addition and Subtraction of Numbers Ones Complement Calculations 4 + 3 7 0100 0011 0111 - 4 + (- 3) - 7 1011 1100 10111 1 1000 End around convey 4 - 3 1 0100 1100 10000 1 0001 - 4 + 3 - 1 1011 0011 1110 End around convey

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Number Systems Addition and Subtraction of Binary Numbers Ones Complement Calculations Why does end-around convey work? Its comparable to subtracting 2 and including 1 n M - N = M + N = M + (2 - 1 - N) = (M - N) + 2 - 1 (M > N) n - M + (- N) = M + N = (2 - M - 1) + (2 - N - 1) = 2 + [2 - 1 - (M + N)] - 1 n-1 M + N < 2 n after end around convey: n = 2 - 1 - (M + N) this is the right shape for speaking to - (M + N) in 1\'s comp!

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Number Systems Addition and Subtraction of Binary Numbers Twos Complement Calculations 4 + 3 7 0100 0011 0111 - 4 + (- 3) - 7 1100 1101 11001 If convey into sign = do then disregard convey if convey in varies from do then flood 4 - 3 1 0100 1101 10001 - 4 + 3 - 1 1100 0011 1111 Simpler expansion plot makes twos supplement the most well-known decision for whole number frameworks inside advanced frameworks

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Number Systems Addition and Subtraction of Binary Numbers Twos Complement Calculations Why can the complete be overlooked? - M + N when N > M: n M* + N = (2 - M) + N = 2 + (N - M) n Ignoring complete is much the same as subtracting 2 n-1 - M + - N where N + M < or = 2 n - M + (- N) = M* + N* = (2 - M) + (2 - N) = 2 - (M + N) + 2 n After disregarding the convey, this is only the correct twos compl. representation for - (M + N)!

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Number Systems Overflow Conditions Add two positive numbers to get a negative number or two negative numbers to get a positive number - 1 - 1 +0 - 2 - 2 1111 0000 +1 1111 0000 +1 1110 0001 - 3 - 3 +2 1101 0010 - 4 - 4 1100 +3 1100 +3 0011 - 5 - 5 1011 0100 +4 0100 +4 1010 - 6 - 6 0101 +5 1001 0110 - 7 - 7 +6 1000 0111 1000 0111 - 8 - 8 +7 - 7 - 2 = +7! 5 + 3 = - 8!

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Number Systems Overflow Conditions 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5 3 - 8 - 7 - 2 7 Overflow 0 1 0 1 0 1 0 1 0 1 0 1 0 5 2 7 - 3 - 5 - 8 No flood No flood Overflow when convey into sign does not equivalent complete

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Networks for Binary Addition Half Adder With twos supplement numbers, option is adequate Ai 0 1 0 1 Ai Bi Sum Carry Bi 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Carry = Ai Bi Sum = Ai Bi + Ai Bi = Ai + Bi An i Sum B Half-snake Schematic i Carry

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Networks for Binary Addition Full Adder Cascaded Multi-bit Adder generally intrigued by including more than two bits this spurs the requirement for the full viper

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Networks for Binary Addition Full Adder S = CI xor A xor B CO = B CI + A CI + A B = CI (A + B) + A B

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Networks for Binary Addition Full Adder/Half Adder Standard Approach: 6 Gates Alternative Implementation: 5 Gates + A B + CI (A xor B) = A B + B CI + A CI

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Networks for Binary Addition Adder/Subtractor A B A B A B A B 3 2 1 0 Sel 0 1 0 1 0 1 0 1 A B A B A B A B Add/Subtract CO + CI CO + CI CO + CI CO + CI S 3 2 1 0 Overflow A - B = A + (- B) = A + B + 1

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Networks for Binary Addition Carry Lookahead Circuits Critical deferral: the proliferation of convey from low to high request organizes late arriving signal two door postponements to figure CO 4 arrange snake last entirety and convey

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Networks for Binary Addition Carry Lookahead Circuits Critical deferral: the engendering of convey from low to high request stages 1111 + 0001 most pessimistic scenario option T0: Inputs to the snake are substantial T2: Stage 0 do (C1) T4: Stage 1 do (C2) T6: Stage 2 do (C3) T8: Stage 3 do (C4) 2 deferrals to process aggregate however last convey not prepared until 6 defers later

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Networks for Binary Addition Carry Lookahead Logic Carry Generate Gi = Ai Bi must produce convey when A = B = 1 Carry Propagate Pi = Ai xor Bi convey in will measure up to do here Sum and Carry can be reexpressed as far as create/spread: Si = Ai xor Bi xor Ci = Pi xor Ci Ci+1 = Ai Bi + Ai Ci + Bi Ci = Ai Bi + Ci (Ai + Bi) = Ai Bi + Ci (Ai xor Bi) = Gi + Ci Pi

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Networks for Binary Addition Carry Lookahead Logic Reexpress the convey rationale as takes after: C1 = G0 + P0 C0 C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0 C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 C4 = G3 + P3 C3 = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0 Each of the convey conditions can be actualized in a two-level rationale arrange Variables are the snake sources of info and convey into stage 0!

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Networks for Binary Addition Carry Lookahead Logic Cascaded Carry Lookahead 4 bit adders with inside convey lookahead second level convey lookahead unit, stretches out lookahead to 16 bits Group P = P3 P2 P1 P0 Group G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0

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Networks for Binary Addition Carry Select Adder Redundant equipment to make convey count go quicker C 0 8 Adder 4-Bit Adder Low [7:4] C 4 C 1 8 4-Bit Adder [7:4] High 1 0 1 0 1 0 1 0 C 4 C 4-Bit Adder ¥ 0 4 2:1 Mux [3:0] C S 8 7 6 5 4 3 2 1 0 process the high request wholes in parallel one expansion accept convey in = 0 alternate expect convey in = 1

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Arithmetic Logic Unit Design Sample ALU Logical and Arithmetic Operations Not all operations seem valuable, however "fall out" of inner rationale

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Arithmetic Logic Unit Design Sample ALU Clever Multi-level Logic Implementation S1 = 0 squares Bi Happens when operations include Ai just Same is valid for Ci when M = 0 Addition happens when M = 1 Bi, Ci to Xor doors X2, X3 S0 = 0, X1 passes A S0 = 1, X1 passes An Arithmetic Mode: Or entryway data sources are Ai Ci and Bi (Ai xor Ci) Logic Mode: Cascaded XORs frame yield from Ai and Bi 8 Gates (yet 3 are XOR)

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Arithmetic Logic Unit Design 74181 TTL ALU

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Lecture Review We have secured: • Binary Number Representation positive numbers a similar contrast is in how negative numbers are spoken to twos supplement most straightforward to handle: one representation for zero, marginally convoluted complementation, basic expansion • Bin

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