Outer Memory Interfaces.


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Outside Memory Interfaces. Numerous microcontrollers (and all microchips) have an outside memory interfaceAllows adding extra memory to the microRequires an outer location/information busPSoC has just a 8-bit RAM transport and a 16-bit Flash ROM busBoth officially full with 256 bytes of RAM and (up to) 64KB of Flash ROMNo outside transport (unless you make one with GPIO)We\'ll utilize the Motorola/Freescale HC1
Transcripts
Slide 1

Outside Memory Interfaces

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External Memory Interfaces Many microcontrollers (and all microchips) have an outer memory interface Allows adding extra memory to the small scale Requires an outside location/information transport PSoC has just a 8-bit RAM transport and a 16-bit Flash ROM transport Both officially full with 256 bytes of RAM and (up to) 64KB of Flash ROM No outside transport (unless you make one with GPIO) We\'ll utilize the Motorola/Freescale HC11 for instance

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HC11 outer memory interface 8-bit information transport Unit of exchange is a solitary byte 16-bit address transport Allows up to 64K aggregate locations (64K bytes) Von Neumann engineering One location space for all memory sorts, including code and information Address space incorporates interior recollections and space for outer recollections

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HC11-A8 Internal Address Map 0000 - 00FF Internal RAM (256 Bytes) Internal Regs (64 Bytes) 1000 - 103F Variants of the HC11 may have all the more/less RAM, EEROM and EPROM Empty spaces have no physical memory by any stretch of the imagination. B600 - B7FF Internal EEROM (512 Bytes) Internal ROM or EPROM (8K Bytes) E000 - FFFF

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Adding Memories 0000 - 00FF Add a 16K x 8 (16Kbyte) memory beginning at area $ 4000 1000 - 103F 16K = 2 14 Range: 00 0000 - 11 1111 External Memory (16K Bytes) 4000 – 7FFF Add to introductory location of $4000 = 01 00 0000  01 00 0000 (4000) to 01 11 1111 (7FFF)  01 xx xxxx B600 - B7FF Internal EEROM (512 Bytes) External Memory (8K Bytes) C000 - DFFF Add a 8K x 8 (8Kbyte) memory beginning at area $ C000 E000 - FFFF Internal ROM or EPROM (8K Bytes) 110 x xxxx

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When Memory isn\'t Memory I/O gadgets frequently have a couple registers Control registers I/O registers If these have an interface that looks like memory, we can associate them to the memory transport Reads/Writes to specific areas will create the fancied change in the I/O gadget controller Almost all outer gadgets can be designed to resemble a memory

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A 0 - A 13 D 0 A 0 - A 10 D 0 - D 7 OE* 6167 SRAM 6116P-4 SRAM CS* WE* Static Memories Real SRAMs arrive in an assortment of sizes, however depend on the same fundamental standards Address input indicates where to peruse/compose Data input/yield contains information to peruse or compose WE* (compose empower): 1 for peruses, 0 for composes OE* (yield empower): 0 empowers the yield drivers CS* (chip select): 0 to choose the chip (empower it) Bitwide 16K x 1-bit: 20 pins Bytewide 2K x 8-bit: 24 pins

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Bitwide versus Bytewide chips give a complete byte at once Perfect for microcontroller frameworks Bitwide chips give one and only piece at once We generally require an entire byte (or more) Requires putting eight or more chips together Common tending to for all chips Each chip gives a solitary piece Example: 32-bit wide memory needs 32 chips Bitwide chips bode well just when we must utilize a considerable measure of chips at any rate (i.e. huge frameworks)

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A 0 - A 12 D 0 - D 7 OE* CS1* HM6264A SRAM CS2 WE* A Simple Memory The HM6264A SRAM is a straightforward memory Static RAM 8-bit information transport 13-bit address transport 2 13 = 8192 bytes Four control signals WE* - declared low on the off chance that this is a compose CS1*, CS2 - Chip Select If both are attested, empowers chip Means Address is substantial OE * - Output Enable Allows memory to drive the information transport

Slide 10

What memory needs... For a memory read , we have to: Place the location on the location pins Assert CS1*, CS2, OE* Wait for the memory to react with the asked for information Look at the worth on the yield pins For a memory compose , we have to: Place address on location pins Assert CS1*, CS2, WE* Place the information on the information pins Hold it there for required measure of time

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Address Bus A 00 - A 15 Data Bus D 00 - D 07 D 0 - D 7 A 0 - A 12 VCC CS2 R/W* WE* 8Kx8 SRAM AV CS1* OE* MicroProc Connecting a memory to a Microprocessor Example for a miniaturized scale with particular 16-bit Address and 8-bit information transports "1" for read, "0" for compose How would we know where memory ought to be situated in location space? Shouldn\'t something be said about genuine microcontroller interfaces? "0" for read, "1" for compose "1" when location is substantial "0" when perused/keep in touch with chip

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CSB* A 15 A 14 CSA* A 13 f A 12 CS* A 11 CS* A 10 Memory 1 Memory 2 A 01 A 00 D 7 D 1 D 0 Selecting a Memory How would we interface two (or more) gadgets without clashing with each other? Select one and only chip at once Available Information for the determination procedure AS, R/W*, Address (A 12 – A 00 go to memory chip) Only the unused location bits ( A 15 - A 13 ) can help us CSA* and CSB* ought to be (elite) elements of A 15 - A 13

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AV CSA* A 15 A 14 A 13 AV CSB* A 15 A 14 A 13 Picking a select capacity CSA* affirmed when A 15 - A 13 = 001 CSB* declared when A 15 - A 13 = 011 CSA* will be attested at whatever point location is 001 x xxxx which is: 001 0 0000 - 001 1 1111 - > $2000-$3FFF CSB* will be stated at whatever point location is 011 x xxxx which is: 011 0 0000 - 011 1 1111 - > $6000-$7FFF

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Full Address Decoding Full address interpreting : Look at all location bits while picking which memory to choose All unused memory bits must be taken a gander at to ensure they\'re the right blend of 0\'s and 1\'s Each gadget/memory has a novel scope of locations in the location space Hints: Put altered (inward) recollections in the guide in front of the pack biggest recollections next Continue down to the littlest gadgets

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(12 bits of location) 4K bytes for ROM 1 Int. EPROM Int. EEROM Int. Regs x x x x x x x x x x x x x x x 1 1 1 x x x x 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 F.A.D. Case 1 – Group recollections together Full Address Decoding 256 bytes for Internal RAM (8 bits of location, $0000 - $00FF) Fixed (inner) recollections 64 bytes for Internal Regs (6 bits of location, $1000 - $103F) 512 bytes for Internal EEROM (9 bits of location, $B600 - $B7FF) 8K bytes for Internal EPROM (13 bits of location, $E000 - $FFFF) 16K bytes for RAM (14 bits of location) $4000 - $7FFF $8000 - $8FFF 1K bytes for ROM 2 (10 bits of location) $9000 - $93FF 4 bytes for ADC (2 bits of location) $9400 - $9403 2 bytes for LCD (1 bit of location) $9404 - $9405 Address Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Int. RAM x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x 0 1 RAM ROM 1 x x x x x x x x x x x x 1 0 0 0 x x x x x x x x x x ROM 2 1 0 0 1 0 0 ADC 1 0 0 1 0 1 0 0 0 0 0 0 0 0 x x LCD 1 0 0 1 0 1 0 0 0 0 0 0 0 1 0 x

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Resulting Address Map 0000 - 00FF Internal RAM (256 Bytes) 1000 - 103F ROM 1 CS=f 1 (A 15 ,A 14 ,A 13 ,A 12 ) Internal Regs (64 Bytes) RAMCS=f 2 (A 15 ,A 14 ) RAM (16K Bytes) 4000-7FFF ROM 2 CS=f 3 (A 15 ,A 14 ,A 13 ,A 12 , A 11 ,A 10 ) ADCCS=f 4 (A 15 ,A 14 ,A 13 ,A 12 , A 11 ,A 10 , A 9 ,A 8 ,A 7 ,A 6 , A 5 ,A 4 ,A 3 ,A 2 ) 8000 – 8FFF ROM 1 (4K Bytes) 9000 - 93FF ROM 2 (1K Bytes) 9400 - 9403 ADC (4 Bytes) 9404 - 9405 LCD (2 Bytes) LCDCS=f 5 (A 15 ,A 14 ,A 13 ,A 12 , A 11 ,A 10 , A 9 ,A 8 ,A 7 ,A 6 , A 5 ,A 4 ,A 3 ,A 2 ,A 1 ) Internal EEROM (512 Bytes) B600 - B7FF Full address unraveling requires a considerable measure of sources of info (loads of equipment) for little gadgets Internal EPROM (8K Bytes)E000-FFFF

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(12 bits of location) 4K bytes for ROM 1 Int. EPROM Int. EEROM Int. Regs x x x x x x x x x x x x x x x 1 1 1 x x x x 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 F.A.D. Case 2 – Place recollections in most minimal address Full Address Decoding 256 bytes for Internal RAM (8 bits of location, $0000 - $00FF) Fixed (inside) recollections 64 bytes for Internal Regs (6 bits of location, $1000 - $103F) 512 bytes for Internal EEROM (9 bits of location, $B600 - $B7FF) 8K bytes for Internal EPROM (13 bits of location, $E000 - $FFFF) 16K bytes for RAM (14 bits of location) $4000 - $7FFF $2000 - $2FFF 1K bytes for ROM 2 (10 bits of location) $0400 - $07FF 4 bytes for ADC (2 bits of location) $0100 - $0103 2 bytes for LCD (1 bit of location) $0104 - $0105 Address Bits 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Int. RAM x x x x x x x x 0 0 0 0 0 0 0 0 x x x x x x x x x x x x x x 0 1 RAM ROM 1 x x x x x x x x x x x x 0 0 1 0 x x x x x x x x x x ROM 2 0 0 0 0 0 1 ADC 0 0 0 0 0 0 0 1 0 0 0 0 0 0 x x LCD 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 x

Slide 18

F.A.D. Talk Full Address Decoding doles out one location to every memory area Other locations make blunders Easy to include more gadgets later Decoding locations is confused Requires loads of equipment (perhaps more than the memory chips themselves) We could have just utilized less bits since there are just five outside gadgets

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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ROM 0 x x x x x x x x x x x RAM 1 x x x x x x x x x x x Partial Address Decoding Place a 2KByte RAM and a 2KByte ROM in location space Simply utilize most noteworthy request bit to pick RAM/ROM (A 15 ) If A 15 is 1, use RAM, if 0, use ROM Requires just a solitary inverter But, shouldn\'t something be said about those unused bits (A 14 - A 11 )? They\'re " don\'t cares " - can be either 0 or 1 Our rationale won\'t take a gander at them

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15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ROM 0 x x x x x x x x x x x RAM 1 x x x x x x x x x x x Multiple Addresses Consider addresses: $1100 = 00 0 1 0001 0000 $3100 = 00 1 0001 0000 They contrast just in bit A 13 But A 13 is a couldn\'t care less piece (it is not decoded) We can\'t differentiate between the two Both locations point to the same memory area!

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There are 16 distinct mixes of bits A 15 , A 14 , A 13 , and A 12 Thus, there are 16 false names for every memory address Aliases for $8014: $8014 $8814 $9014 $9814 $A014 $A814 $B014 $B814 $C014 $C814 $D014 $D814 $E014 $E814 $F014 $F814 Aliases 15 14

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