PAPI Assessment.


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PAPI Assessment. Patricia J. Teller , Maria G. Aguilera, Thientam Pham, and Roberto Araiza ( Leonardo Salayandia, Alonso Bayona, Manuel Nieto, and Michael Maxwell) College of Texas-El Paso . Bolstered by the Bureau of Barrier PET Project. Fundamental Targets.
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PAPI Evaluation Patricia J. Teller , Maria G. Aguilera, Thientam Pham, and Roberto Araiza ( Leonardo Salayandia, Alonso Bayona, Manuel Nieto, and Michael Maxwell) University of Texas-El Paso . Bolstered by the Department of Defense PET Program SC 2003, Phoenix, AZ – November 17-20, 2003

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Main Objectives Provide DoD clients with an arrangement of documentation that empowers them to effortlessly gather, break down, and decipher equipment execution information that is very pertinent for examining and enhancing execution of utilizations on HPC stages. SC 2003, Phoenix, AZ – November 17-20, 2003

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Evaluation: Objectives Understand and clarify checks acquired for different PAPI measurements Determine reasons why tallies may be not the same as what is normal Calibrate checks, barring PAPI overhead Work with merchants and/or the PAPI group to settle lapses Provide DoD clients with data that will permit them to adequately utilize gathered execution information SC 2003, Phoenix, AZ – November 17-20, 2003

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Evaluation: Methodology - 1 Micro-benchmark : outline and actualize a smaller scale benchmark that encourages occasion tally prediction P rediction : foresee occasion checks utilizing apparatuses and/or numerical models D ata accumulation - 1 : gather equipment reported occasion numbers utilizing PAPI Data accumulation - 2 : gather anticipated occasion tallies utilizing a test system (not generally fundamental or conceivable) SC 2003, Phoenix, AZ – November 17-20, 2003

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Evaluation: Methodology - 2 Comparison : think about anticipated and equipment reported occasion checks Analysis : break down results to recognize and potentially evaluate contrasts Alternate methodology : when investigation shows that forecast is unrealistic, utilize a substitute intends to either confirm reported occasion tally exactness or exhibit that the reported occasion tally appears to be sensible SC 2003, Phoenix, AZ – November 17-20, 2003

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Example Findings - 1 Some equipment reported occasion numbers mirror expected conduct , e.g., number of gliding point guidelines on the MIPS R10K and R12K. Other equipment reported occasions can be aligned , by subtracting that an occasion\'s piece tally connected with the interface ( overhead or predisposition lapse ), to reflect expected conduct , e.g., number of burden directions on the MIPS and POWER processors and guidelines finished on the POWER3. Sometimes, compiler enhancements impact occasion checks , e.g., the quantity of drifting point guidelines on the IBM POWER stages. SC 2003, Phoenix, AZ – November 17-20, 2003

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Example Findings - 2 Very-long direction words can influence occasion checks, e.g., on the Itanium structural planning the quantity of guideline store misses and directions resigned are expanded by no-operations used to form long guideline words. The occasion\'s meaning number may be non-standard and, in this way, the related execution information may be deluding , e.g., direction store hits on the POWER3. The many-sided quality of equipment elements and absence of documentation can make it hard to see how to tune execution in light of data gathered from occasion counts—example: information prefetching, page walker. SC 2003, Phoenix, AZ – November 17-20, 2003

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Example Findings - 3 Although we have not possessed the capacity to focus the calculations utilized for prefetching , the inventiveness and execution of these components is striking. Sometimes, a larger number of directions are finished than issued on the R10K . The DTLB miss rely on the POWER3 shifts relying on the system used to allot memory ( i.e., static, calloc or malloc). Equipment SQRT on POWER3 not checked altogether skimming point operations unless consolidated with another gliding point operation . SC 2003, Phoenix, AZ – November 17-20, 2003

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Publications Papers DoD Users Group Conference (with Shirley Moore), June 2003. LACSI 2002 (with Shirley Moore), October 2002. DoD Users Group Conference (with individuals from PAPI group), June 2002. “Hardware Performance Metrics and Compiler Switches: What you see is not generally what you get,” with Luiz Derose, submitted for production. Publications “Hardware Performance Counters: Is the thing that you see, what you get?, Poster SC2003. Presentations PTools Workshop , September 2002. Gathering Presentations for Papers above. SC 2003, Phoenix, AZ – November 17-20, 2003

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Calibration Example - 1 Instructions finished PAPI overhead: 139 on POWER3-II SC 2003, Phoenix, AZ – November 17-20, 2003

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Calibration Example - 2 Instructions finished PAPI overhead: 141 for little smaller scale benchmarks SC 2003, Phoenix, AZ – November 17-20, 2003

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RIB/OKC for Evaluation Resources Object-arranged information model to store benchmarks, results and examinations Information sorted out for usability by associates outer to PCAT To be web-available to individuals Objects connected between them as proper Benchmark General depiction of a benchmark Case Specific execution and results Machine Description of stage Organization Contact data SC 2003, Phoenix, AZ – November 17-20, 2003

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PCAT RIB/OKC Data Repository Example Benchmark name: DTLB misses Development date: 12/2002 Benchmark sort: Array Abstract: Code navigates however a variety of whole numbers once at customary steps of PAGESIZE. The aim is to make necessary misses on every cluster access. Information parameters are: Page size (bytes) and exhibit size (bytes). The quantity of misses typically expected ought to be: Array Size/Page Size. Records included: dtlbmiss.c , dtlbmiss.pl About included documents: dtlbmiss.c, benchmark source code in C, requires pagesize and arraysize parameters for data and yields PAPI occasion tally. dtlbmiss.pl, perl script that executes the benchmark 100 times for expanding arraysize parameters and spares benchmark yield to content document. Script ought to be redone for pagesize parameter and arraysize range. Connections to documents SC 2003, Phoenix, AZ – November 17-20, 2003

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PCAT RIB/OKC Example Case Object Name: DTLB misses on Itanium Date: 12/2002 Compiler and alternatives: gcc ver 2.96 20000731 (Red Hat Linux 7.1 2.96-101) –O0 PAPI Event: PAPI_TLB_DM, Data TLB misses Native Event: DTLB_MISSES Experimental approach: Ran benchmark 100 times with perl script, midpoints and standard deviations reported Input parameters utilized: Page size = 16K, Array size = 16K – 160M (additions by products of 10) Platform utilized: HP01.cs.utk.edu (Itanium) Developed by: PCAT Benchmark utilized: DTLB misses Links to different articles SC 2003, Phoenix, AZ – November 17-20, 2003

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PCAT RIB/OKC Example Case Object Results rundown: Reported checks intently coordinate the anticipated tallies, demonstrating contrasts near 0% even in the cases with a little number of information references, which may be more defenseless to outside bother. The checks demonstrate that prefetching is not performed at the DTLB level. Included documents and portrayal: dtlbmiss.itanium.c : Source code of benchmark, instrumented with PAPI to tally PAPI_TLB_DM dtlbmiss.itanium.pl : Perl script used to run the benchmark dtlbmiss.itanium.txt : Raw information got, every segment contains results for a specific cluster size, every case is run 100 times (i.e., 100 lines included) dtlbmiss.itanium.xls : Includes crude information, midpoints of runs, standard deviations and chart of % distinction in the middle of reported and anticipated considers dtlbmiss.itanium.pdf : Same dtlbmiss.itanium.xls SC 2003, Phoenix, AZ – November 17-20, 2003

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Contributions Infrastructure that encourages client access of equipment execution information that is profoundly pertinent for breaking down and enhancing the execution of their applications on HPC stages. Data that permits clients to successfully utilize the information with certainty. SC 2003, Phoenix, AZ – November 17-20, 2003

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QUESTIONS? SC 2003

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