Part 15 Multistage Enhancers.


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Jaeger/Blalock7/1/03. Microelectronic Circuit DesignMcGraw-Hill. Section Goals. Comprehend investigation and outline of air conditioning coupled multistage intensifiers including voltage pick up, information and yield resistances and little flag limitations.Understand examination and outline of dc-coupled multistage amplifiers.Discuss attributes of Darlington setup and cascode amplifier.Explore dc and air conditioning properties o
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´╗┐Section 15 Multistage Amplifiers Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock Microelectronic Circuit Design McGraw-Hill Chap 15 - 1

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Chapter Goals Understand investigation and outline of air conditioning coupled multistage enhancers including voltage pick up, info and yield resistances and little flag constraints. Comprehend examination and configuration of dc-coupled multistage intensifiers. Talk about attributes of Darlington setup and cascode enhancer. Investigate dc and air conditioning properties of differential speakers. Comprehend fundamental three-phase operation amp. Investigate outline of class-A, class-B, class-AB yield stages. Talk about attributes and outline of electronic current sources. Keep understanding the utilization of SPICE in circuit investigation. Microelectronic Circuit Design McGraw-Hill Chap 15 - 2

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AC-coupled Amplifiers: Circuit Microelectronic Circuit Design McGraw-Hill Chap 15 - 3

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AC-coupled Amplifiers: Description MOSFET M 1 working in C-S arrangement gives high info resistance and moderate voltage pick up. BJT Q 2 in C-E arrangement, the second stage, gives high pick up. BJT Q 3 , an emitter-devotee gives low yield resistance and cradles the high pick up stage from the moderately low load resistance. Predisposition resistors are supplanted by Input and yield of general enhancer is air conditioning coupled through capacitors C 1 and C 6 . Sidestep capacitors C 2 and C 4 are utilized to get most extreme voltage pick up from the two transforming intensifiers. Interstage coupling capacitors C 3 and C 5 exchange air conditioning signals between enhancers yet give seclusion at dc, and anticipate Q-purposes of the transistors from being influenced. Microelectronic Circuit Design McGraw-Hill Chap 15 - 4

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AC-coupled Amplifiers: Equivalent Circuits AC Equivalent Small-flag Equivalent DC Equivalent Microelectronic Circuit Design McGraw-Hill Chap 15 - 5

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AC-coupled Amplifiers: Input Resistance and Voltage Gain Microelectronic Circuit Design McGraw-Hill Chap 15 - 6

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AC-coupled Amplifiers: Output Resistance To discover yield resistance, test voltage is connected at intensifier yield. Microelectronic Circuit Design McGraw-Hill Chap 15 - 7

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AC-coupled Amplifiers: Current and Power Gain Input current conveyed to enhancer from source is and current conveyed to stack by speaker is Microelectronic Circuit Design McGraw-Hill Chap 15 - 8

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AC-coupled Amplifiers: Input Signal Range For first stage, For second stage, For third stage, all in all, Microelectronic Circuit Design McGraw-Hill Chap 15 - 9

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AC-coupled Amplifiers: Methods to Improve Voltage Gain of C-S intensifier is conversely corresponding to square base of channel current, so voltage addition could be expanded by decreasing I D 1 while keeping up a steady voltage drop crosswise over R D 1 . Signal extent could be enhanced by expanding current in yield stage and voltage drop crosswise over R E 3 . Q 1 could be supplanted with a FET. This could bring about increase misfortune in third stage since addition of C-D intensifier is regularly < that of a C-C stage. Be that as it may, this misfortune could be made up by enhancing addition of first and second stages. Microelectronic Circuit Design McGraw-Hill Chap 15 - 10

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Common-Emitter Cascade If addition is restricted by interstage resistances, every stage has an increase of about - 10 V CC and general increase is: If addition is constrained by info resistance of transistors, it is given by: Normally as sign and power levels more often than not increment in each progressive phase of generally enhancers. Since b o < 10 V CC , this case frequently speaks to as far as possible. To accomplish most extreme increase, a few C-E stages can be fell. For the last stage, For every single other stage, Microelectronic Circuit Design McGraw-Hill Chap 15 - 11

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Direct-coupled Amplifiers: Circuit Bypass capacitors-C 2 and C 4 influence pick up at low frequencies however don\'t characteristically keep the enhancer from working at dc. Symmetrical force supplies are utilized to set Q-point voltages at information and yield to around zero. Substituting pnp or p - channel and npn or n - channel transistors are utilized from stage to stage to take most extreme preferred standpoint of accessible force supply voltage. Coupling capacitors in arrangement with sign way C 1 , C 3 , C 5 , and C 6 are wiped out as they keep the intensifier from giving addition at dc or low frequencies. Extra inclination resistors in individual stages are likewise evacuated, making plan less costly. Microelectronic Circuit Design McGraw-Hill Chap 15 - 12

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Direct-coupled Amplifiers: DC Analysis So, I D = 6.66. Mama (which would deliver 10.7 V drop crosswise over R S 1 and cut off FET) or I D =5.29 mA (right esteem). I B 2 << I D , which is sufficient to squeeze off M 1 . b F 2 =150, so I C 2 =1.83 mA and I B 2 = 12.2 m A. I B 3 << I C 2 , which < 0.7 V , so Q 2 is in dynamic area. Voltage at channel of M 1 gives base inclination to Q 2 and voltage at gatherer of Q 2 gives base predisposition to Q 3 . All transistors work in dynamic locale regardless of direct association between stages. Microelectronic Circuit Design McGraw-Hill Chap 15 - 13

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Direct-coupled Amplifiers: DC Analysis (contd.) b F 3 = 80, so I C 3 =3.94 mA and I B 3 = 49.3 m An accordingly Q 3 is in dynamic district. There is a balanced voltage of 0.4 V at yield and a nonzero dc current exists in 250 W load resistor. In a perfect outline, balance voltage would be zero and no dc current would show up in burden. Taking into account Q-point values, little flag parameters can be ascertained. Microelectronic Circuit Design McGraw-Hill Chap 15 - 14

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Direct-coupled Amplifiers: AC Analysis Dc coupling requires less segments than air conditioning coupling yet Q-purposes of different stages get to be reliant. In the event that Q-purpose of one phase shifts, Q-purposes of every single other stage may likewise move . Estimations of interstage capacitors are higher than those in air conditioning coupled speaker because of nonattendance of predisposition resistors. General qualities are like those in air conditioning coupled intensifier as Q-focuses and little flag parameters of transistors are comparative Microelectronic Circuit Design McGraw-Hill Chap 15 - 15

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Direct-coupled Amplifiers: Darlington Circuit AC Analysis: For the composite transistor, Darlington circuit carries on like the single transistor yet has a present addition given by the result of current increases of individual transistors. DC Analysis: For b F 1 , b F 2 >>1, V BE of composite transistor = 2 diode voltage drops. So V CE >( V BE 1 + V BE 2 ) . Microelectronic Circuit Design McGraw-Hill Chap 15 - 16

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Direct-coupled Amplifiers: Cascode Circuit AC Analysis: For the composite transistor, Cascode circuit is course association of C-E and C-B enhancers, utilized as a part of high pick up intensifiers and high yield resistance current sources. DC Analysis: For a high current increase, For forward-dynamic operation of Q 2 , Microelectronic Circuit Design McGraw-Hill Chap 15 - 17

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Differential Amplifiers Differential-mode yield voltage is the voltage distinction between authorities, channels of the two transistors.Ground referenced yields can likewise be taken from gatherer/channel. Perfect differential enhancer utilizes superbly coordinated transistors. Differential amplifiers,also considered the C-C/C-B course, dispose of the detour capacitors and in addition the outer coupling capacitors at the info and yield of direct-coupled intensifiers. Every circuit has two data sources. Microelectronic Circuit Design McGraw-Hill Chap 15 - 18

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Bipolar Differential Amplifiers: DC Analysis Terminal streams are additionally equivalent. Both sources of info are set to zero, emitters are associated together. In the event that transistors are coordinated, Microelectronic Circuit Design McGraw-Hill Chap 15 - 19

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Small-Signal Transfer Characteristic The present switch is an advanced utilization of the differential intensifier. Substantial sign exchange normal for differential speaker is given by: Even-arrange mutilation terms are eliminated.This expands signal-taking care of capacity of differential pair. For little flag operation, liner term must be predominant. Thus, we set the third-arrange term to be one-tenth the direct term. Microelectronic Circuit Design McGraw-Hill Chap 15 - 20

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Bipolar Differential Amplifiers: DC Analysis (Example) Problem: Find Q-purposes of transistors in the differential intensifier. Given information: V CC = V EE =15 V, R EE = R C =75k W , b F =100 Analysis: Due to symmetry, both transistors are one-sided at Q-point (94.4 m A, 8.62V) Microelectronic Circuit Design McGraw-Hill Chap 15 - 21

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Bipolar Differential Amplifiers: AC Analysis A dd = differential-mode pick up A compact disc = regular mode to differential-mode transformation pick up A cc = normal mode pick up A dc = differential mode to basic mode change pick up For perfect symmetrical intensifier, An album = A dc = 0. Simply differential-mode input gives absolutely differential-mode yield and the other way around. Circuit examination is finished by superposition of differential-mode and normal mode signal bits. Microelectronic Circuit Design McGraw-Hill Chap 15 - 22

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Bipolar Differential Amplifiers: Differential-mode Gain and Input Resistance Emitter hub in differential enhancer speaks to virtual ground for differential-mode input signals. Yield signal voltages are: Microelectronic Circuit Design McGraw-Hill Chap 15 - 23

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Bipolar Differential Amplifiers: Differential-mode Gain and Input Resistance (contd.) Differential-mode pick up for adjusted yield, is: If either v c1 or v c2 is utilized alone as yield, yield is said to be single-finished. Differential-mode input resistance is little flag resistance displayed to differential-mode input voltage between the two transistor bases. In the event that v id =0, . For single-finished yields, Microelectronic Circuit Des

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