PC Supported Configuration Idea to Silicon.


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PC Supported Configuration Idea to Silicon Victor P. Nelson ASIC Outline Stream Behavioral Model VHDL/Verilog Check Capacity Union DFT/BIST and ATPG Entryway Level Netlist Confirm Work Full-custom IC Test vectors Transistor-Level Netlist Confirm Capacity and Timing
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PC Aided Design Concept to Silicon Victor P. Nelson

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ASIC Design Flow Behavioral Model VHDL/Verilog Verify Function Synthesis DFT/BIST & ATPG Gate-Level Netlist Verify Function Full-custom IC Test vectors Transistor-Level Netlist Verify Function & Timing Standard Cell IC & FPGA/CPLD DRC & LVS Verification Physical Layout Map/Place/Route Verify Timing IC Mask Data/FPGA Configuration File

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Mentor Graphics CAD Tools (select from “eda” list in client setup on the Sun system) ICFlow2007.2 – For custom & standard cell IC plans IC stream apparatuses (Design Architect-IC, IC Station, Caliber) Digital/simple/blended recreation (Modelsim,ADVance MS,Eldo,MachTA) HDL Synthesis (Leonardo) DFT/2006.3 ATPG/DFT/BIST devices (DFT Advisor, Flextest, Fastscan) Modelsim/6.3c (HDL Simulation) FPGA/2004 (FPGA Advantage, Modelsim, Leonardo) *Xilinx/ISE8.2i (Xilinx FPGA/CPLD - back end outline) *QuartusII/5.0 (Altera FPGA/CPLD - back end plan) *Ims/6.2 (IMS chip analyzer) * Vendor-Provided (Not Mentor Graphics) Tools

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Mentor Graphics ASIC Design Kit (ADK) Technology documents & standard cell libraries AMI: ami12, ami05 (1.2, 0.5 μ m) TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μ m) IC stream & DFT device bolster records: Simulation VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS) Analog (SPICE) models (Eldo/Accusim) Post-format timing (Mach TA) Digital schematic ( Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018) Synthesis to sexually transmitted disease. cells (LeonardoSpectrum) Design for test & ATPG (DFT Advisor, Flextest/Fastscan) Schematic catch (Design Architect-IC) IC physical configuration (standard cell & custom) Floorplan, place & course (IC Station) Design principle check, format versus schematic, parameter extraction (Caliber)

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Xilinx/Altera FPGA/CPLD Design Simulate outlines in Modelsim Behavioral models (VHDL,Verilog) Synthesized netlists (VHDL, Verilog) Requires “primitives” library for the objective innovation Synthesize netlist from behavioral model Leonardo has libraries for most FPGAs Xilinx ISE has its own blend device Vendor instruments for back-end outline Map, spot, course, arrange gadget, timing examination, produce timing models Xilinx Integrated Software Environment (ISE) Altera Quartus II & Max+Plus2 Higher level apparatuses for framework plan & administration Mentor Graphics FPGA Advantage Xilinx Platform Studio : SoC outline, IP administration, HW/SW codesign

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Behavioral Design & Verification (basically innovation free) VHDL Verilog SystemC Create Behavioral/RTL HDL Model(s) VHDL-AMS Verilog-A Simulate to Verify Functionality ModelSim (computerized) ADVance MS (simple/blended sign) Leonardo Spectrum, Xilinx ISE (computerized) Synthesize Circuit Technology Libraries Post-Layout Simulation, Technology-Specific Netlist to Back-End Tools

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ADVance MS Simulation System ADVance MS “kernel” bolsters: VHDL & Verilog: advanced (by means of ModelSim) VHDL-AMS & Verilog-A: simple/blended sign Eldo/SPICE: simple (through Eldo) Eldo RF/SPICE: simple RF (by means of Eldo RF) Mach TA/SPICE: rapid simple/timing Invoke remain solitary or from Design Architect-IC

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ADVance MS Digital, Analog, Mixed-Signal Simulation VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Netlists VITAL SPICE models Xilinx simprims Design_1 Design_2 IEEE 1164 Working Library Resource Libraries ADVance MS Input Stimuli Simulation Setup Mixed Signal (VHDL-AMS, Verilog-An) EZwave or Xelga Eldo, Eldo RF ModelSim Analog (SPICE) Mach TA Mach PA View Results Digital (VHDL,Verilog)

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Example: 4-bit twofold counter VHDL model (count4.vhd) Create working library: vlib work vmap work Compile: vcom count4.vhd Simulate: vsim count4(rtl) ModelSim reenactment control inputs ModelSim “Macro” (count4_rtl.do) OR, VHDL testbench ModelSim results posting or waveform

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- count4.vhd 4-bit parallel-load synchronous counter LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; - combination libraries ENTITY count4 IS PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); END count4; ARCHITECTURE rtl OF count4 IS SIGNAL int : unsigned(3 downto 0); BEGIN PROCESS(clear, clock, empower) BEGIN IF (clear = \'1\') THEN int <= "0000"; ELSIF (clock\'EVENT AND clock=\'1\') THEN IF (empower = \'1\') THEN IF (load_count = \'1\') THEN int <= D; ELSE int <= int + "01"; END IF; END IF; END IF; END PROCESS; Q <= int; END rtl;

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Test boost: Modelsim “do” record: count4_rtl.do include wave/clock/clear/empower/load_count/D/Q include list/clock/clear/empower/load_count/D/Q power/clock 0, 1 10 - rehash 20 power/clear 0, 1 5, 0 10 power/empower 0, 1 25 power/load_count 0, 1 20, 0 35, 1 330, 0 350 power/D 10#5 0, 10#9 300 run 400

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Testbench: count4_bench.vhd Alternative to “do” document LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY count4_bench is end count4_bench; ARCHITECTURE test of count4_bench is segment count4 PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); end part; for all: count4 use element work.count4(behavior); signal clk : STD_LOGIC := \'0\'; signal clr, en, ld: STD_LOGIC; sign racket, qout: unsigned(3 downto 0); start UUT: count4 port map(clk,clr,en,ld,din,qout); clk <= not clk after 10 ns; P1: procedure start commotion <= "0101"; clr <= \'1\'; en <= \'1\'; ld <= \'1\'; sit tight for 10 ns; clr <= \'0\'; sit tight for 20 ns; ld <= \'0\'; sit tight for 200 ns; end procedure; end; Could likewise check results & “assert” mistake messages

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Count4 – Simulation waveform Clear Counting Parallel Load

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ADVance MS : blended sign reproduction A/D converter computerized simple VHDL-AMS

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ADVance MS: blended Verilog-SPICE Verilog top (test seat) SPICE subcircuit

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Automated Synthesis with Leonardo Spectrum VHDL/Verilog Behavioral/RTL Models Technology Synthesis Libraries FPGA Leonardo Spectrum (Level 3) Design Constraints ASIC ADK AMI 0.5, 1.2 TSMC 0.35, 0.25 Level 1 – FPGA Level 2 – FPGA + Timing Level 3 – ASIC + FPGA Technology-Specific Netlist VHDL, Verilog, SDF, EDIF, XNF

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Leonardo – ASIC Synthesis Flow

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Leonardo amalgamation technique Invoke leonardo Select & load an innovation library (ASIC or FPGA) ASIC > ADK > TSMC 0.35 micron Read info VHDL/Verilog file(s): count4.vhd Enter any limitations (clock freq, delays, and so on.) Optimize for territory/delay/exertion level Write yield file(s) count4_0.vhd - VHDL netlist count4.v - Verilog netlist (for IC design) count4.sdf - Standard postponement organization record (for timing) count4.edf - EDIF netlist (for Xilinx/Altera FPGA)

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Leonardo-incorporated netlist count4_0.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; library adk; use adk.adk_components.all; - ADDED BY VPN element count4 is port ( check : IN std_logic ; clear : IN std_logic ; empower : IN std_logic ; load_count : IN std_logic ; D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ; end count4 ; structural engineering netlist of count4 is - rtl changed to netlist by VPN signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189: std_logic ; start Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ; Q_0_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear); ix127 : mux21_ni port guide ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable ); ix9 : oai21 port guide ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 ); ix170 : nand02 port guide ( Y=>nx169, A0=>D(0), A1=>load_count); Q_1_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear); ix137 : mux21_ni port guide ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> empower); ix29 : ao22 port guide ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22); ix15 : or02 port guide ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR); ix23 : aoi21 port guide ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count); Q_2_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); ix147 : mux21_ni port guide ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> empower); ix49 : oai21 port guide ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189); ix182 : aoi21 port guide ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR); ix184 : nand02 port guide ( Y=>nx183, A0=>nx185, A1=>nx187); ix186 : inv01 port guide ( Y=>nx185, A=>load_count); ix188 : nand03 port guide ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR); ix190 : nand02 port guide ( Y=>nx189, A0=>D(2), A1=>load_count); Q_3_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); ix157 : mux21_ni port guide ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> empower); ix63 : mux21_ni

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