Power Administration of Blaze Memory for Compact Gadgets.


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Interest for compact gadgets have expanded. Power utilization is major ... Progressed electronic chips permits to have diverse voltage levels in ...
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Power Management of Flash Memory for Portable Devices Thayalan Selvam Suganthan Vivekananthan Thushitha Kanagaratnam ELG 4135, Fall 2006 Faculty of Engineering, University of Ottawa November 1, 2006

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Outline Introduction to Flash Memory Why power enhancement? Dynamic Voltage Scaling Simulation Conclusion

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Flash Memory Non-unpredictable information stockpiling gadgets Storage of caught electrons in Cells have diverse legitimate capacities: NOR or NAND NOR streak memory:- Faster read time longer delete and compose times NAND streak memory:- Longer read time Faster eradicate and compose times

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Usage of Flash Memory Computer\'s BIOS chip Digital cameras Mp3 players Memory Stick PCMCIA Type I and Type II memory cards PDA

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Advantages of Flash Memory Maintain put away data without force source High stockpiling limit and similarity No physical circle to spun as in hard plates High preparing speed :- Virtually the rate is same as light\'s velocity. Restricting element is USB 2.0 Compact size :- 2mm to 3mm in width

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Why Power Optimization ? Interest for versatile hardware gadgets have expanded Power utilization is real obstruction in any portable compact gadgets. Fundamental assignment to keep up low power utilization Low power expands the execution and makes the gadgets strong

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Limitations on Power Optimization Low power utilization Supply voltage Clock recurrence Performance time Circuit defer Low cost

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System Block Diagram of a Portable Device (mp3 player)

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Power Optimization Algorithms Dynamic Voltage Scaling Static Voltage Scaling Voltage Clock Scaling

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Dynamic Voltage Scaling Algorithm Allows gadgets to change voltage and velocity Uses distinctive voltage level for project, compose and eradicate Uses high voltage when the work burden is high Uses low voltage when the work burden is low

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Advantages of Dynamic Voltage Scaling Algorithm Advanced electronic chips permits to have diverse voltage levels in gadgets Intelligence power administration permits to protract the operational time by working the gadgets at low power level , at whatever point conceivable Save the battery power

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Our Contributions Literature look on different force administration calculations Selected one Dynamic Voltage Scaling calculation: Dynamic Voltage Adjustment calculation We proposed another form of existing element voltage alteration calculation The execution of the new calculation is contrasted and the current calculation

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Dynamic Voltage Adjustment (DVA) Algorithm NOR Flash Memory: Block read utilizes steady voltage level. Power administration is required just for compose and delete operations Each undertakings have due date time This calculation taking into account Earliest Deadline First (EDF) calculation. That is most punctual due date undertakings are planned First K assignments are worked at high voltage level and rest of the errands are at low voltage level This calculation ensure that K is minimized

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DVA (Cont\'d.) Let S = {R 1 , R 2 … R n } be the pending solicitation for glimmer memory and are masterminded by due date T 1 , T 2 ,… T n. Here, T 1 < T 2 <… T n pseudo code For i=1:n Schedule assignment R i at low voltage Find all out time if all out time > T i conform first K undertakings at high voltage (ensure that k is minimized) end End

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New form of DVA Pseudo code of proposed calculation For i=1:n Schedule errand R i at low voltage Find all out time if complete time > T i modify most limited K assignments at high voltage (ensure that k is minimized) end End

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Simulation Set Up Considered NOR Flash memory: - Read time is consistent. Compose and Erase are considered Block Size: 64 kb Two levels of working voltages: 5V and 12V

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Simulation Results (Voltage Level) First 5 assignments are worked at high voltage Rest of the errands are worked at low voltage This calculations ensure that the quantity of high voltage undertakings are minimized Proposed calculation set briefest k undertakings at high voltage

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Simulation Results (Power Consumption) This chart analyzes the force utilization of the calculations Graph obviously demonstrates the execution of the DVA (Dynamic Voltage Adjustment) calculation and the proposed calculation However, proposed calculation have 6.475% change contrast with existing DVA calculation

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Conclusion Dynamic Voltage Adjustment calculation is viewed as The reenactment results indicates effectiveness of the force administration calculation Dynamic Voltage Adjustment calculation is valuable in the usage of versatile gadgets which spares battery power We picked up a decent information in different force administration calculations.

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Future work! In this connection, we considered heuristic methodologies for force administration and subsequently the arrangement is close ideal Explore effective enhancement devices to discover careful ideal arrangement Online entry of errands can be joined Consider multi voltage levels . (This undertaking we have considered two voltage levels). Be that as it may, voltage levels can\'t be expanded the same number of since the electronic circuit\'s impediments

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References [1] Tanzawa T, Takano Y, Taura T, Atsumi S. "A Novel Bit-Line Direct-Sense Circuit that uses a criticism framework for High-Speed Flash Memory." Research Institute of Electrical Communication, Tohoku University, Japan. January 2006 [2] Li-Pin Chang, Tei Wei Kuo, Shi-Wu Lo. " A Dynamic-Voltage-Adjustment in decreasing the force utilization of glimmer memory for convenient gadgets." Taipei,Taiwan. [3] Yehua Du, Ming Cai, Jinxiang Dong. "Dynamic Voltage Scaling of Flash Memory Storage Systems for Low-Power Real-Time Embedded Systems." Zhejiang University, Hangzhou, China

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Thank You Special Thanks to Dr. Habash and TA\'s for help and backings. Questions?????

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