Prologue to CMOS Logic Circuits .


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CMOS NFET and PFET Transistors. N channel gadget: fabricated specifically in the P substrate with N-doped source and deplete intersections and typically N-doped entryway conductorRequires positive voltage connected to door and channel (concerning source) for electrons to spill out of source to deplete (considered as positive channel current)P channel gadget: manufactured in a N-well (a profound N-sort intersection diffused into the P
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Slide 1

Prologue to CMOS Logic Circuits CMOS remains for Complementary Metal Oxide Semiconductor Complementary : there are N-sort and P-sort transistors. N-sort transistors utilize electrons as the present bearers. P-sort transistors utilize gaps as the present transporters. Electrons are free transporters in the conduction band with vitality of Ec or simply over the conduction band edge. Free electrons are created by doping the silicon with a N-sort contamination, for example, phosphorous or arsenic. A gap is a present transporter because of the nonappearance of an electron in a covalent bond state, i.e. a missing electron which would somehow or another be a piece of a silicon-to-silicon bond. Gaps are free transporters in the valence band with vitality of Ev or just underneath the valence band edge. Openings are created by doping the silicon with a P-sort polluting influence, for example, boron. Metal : the entryway of the transistor was made of aluminum metal in the good \'ol days, however is made of polysilicon today (for as far back as 25 years or more). Oxide : silicon dioxide is the material between the entryway and the channel Semiconductor : the semiconductor material is silicon, a sort IV component in the intermittent outline. Every silicon iota bonds to four other silicon iotas in a tetrahedral precious stone structure. R. W. Knepper SC571, page 1-1

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CMOS NFET and PFET Transistors oxide door entryway N + N N+ P+ source P substrate deplete N well N channel gadget P channel gadget N channel gadget: constructed straightforwardly in the P substrate with N-doped source and deplete intersections and regularly N-doped door conductor Requires positive voltage connected to entryway and deplete (concerning source) for electrons to spill out of source to deplete (considered as positive deplete current) P channel gadget: worked in a N-well (a profound N-sort intersection diffused into the P substrate) with P-doped source and deplete intersections and N or P-doped entryway Requires negative voltage connected to entryway and deplete (as for source) for electrons to spill out of deplete to source (considered as negative deplete current) R. W. Knepper SC571, page 1-2

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oxide entryway N + N N+ P substrate deplete source N channel gadget oxide door P+ source deplete N well P channel gadget N-FET and P-FET Devices as Switches NFET Device: positive voltage ("1" or high) on entryway with respect to source turns gadget ON and permits positive current to spill out of deplete to source (switch shut) zero volts on entryway ("0" or low) turns gadget OFF (open circuit) Source (versus deplete) is the most negative terminal PFET Device: Negative voltage ("0" or low) on door in respect to source turns gadget ON and permits (negative) current to spill out of deplete to source (closes switch) Zero volts on door in respect to source ("1" or high) turns gadget OFF (closes switch) source (versus deplete) is the best terminal door source deplete substrate N-FET gadget schematic entryway source deplete substrate R. W. Knepper SC571, page 1-3 P-FET gadget schematic

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Simple CMOS Circuits: The Inverter Gate Vdd Inverter Schematic PFET source The most straightforward integral MOS (CMOS) circuit is the inverter: NFET & PFET doors are associated together as the info NFET & PFET channels are associated together as the yield NFET & PFET sources are associated with Gnd and Vdd, separately. NFET substrate is typically associated with Gnd for all NFET gadgets in the circuit PFET well is ordinarily associated with Vdd (best voltage in circuit) for all PFET gadgets Operation: If Vin is down (0 volts), NFET is OFF and PFET is ON pulling Vout to Vdd (high = 1) If Vin is up (at Vdd), NFET is ON hard and PFET is OFF pulling Vout low to Gnd ("0") With Vin at 0 or Vdd, no dc current streams in inverter P-FET PFET deplete Vout Vin NFET deplete N-FET NFET source Gnd Inverter Symbol R. W. Knepper SC571, page 1-4

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Simple CMOS Circuits: The Transmission Gate X entryway Schematic Vgc = Vg P-FET Circuit topology: N and P gadgets with sources and depletes associated in parallel. Vg is the control motion for the N gadget; Vgc (supplement of Vg) is the control motion for the P gadget. Operation: When Vg is high (at Vdd) and Vgc is in this manner low (at Gnd), the NFET and PFET are both ON. (Contingent on the gadgets\' source possibilities, one might be ON more emphatically than the other.) The switch is in this way CLOSED and Vout will be a similar rationale level as Vin. At the point when Vg is low (at Gnd) and Vgc is high (at Vdd), both gadgets are OFF. The switch is along these lines OPEN and Vout will be autonomous of Vin (high Z association). Vdd Vin Vout Gnd N-FET Vg - s X-entryway Symbols in out s - s in out s - s in out s R. W. Knepper SC571, page 1-5

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Vout = A B = A + B A Vout B Simple CMOS Circuits: 2-way NAND Vdd T3 Circuit Topology: T1 and T2 are N-FET gadgets associated in arrangement; T3 and T4 are P-FET gadgets associated in parallel with their sources at Vdd and their channels at Vout. Inputs An and B are associated with the entryways of T1 & T3 and T2 & T4, individually. T2, T3, & T4 work as "grounded source" gadgets, however T1 has its source by and large above Gnd potential. Operation: If both An and B are high (at Vdd), both T1 and T2 are ON hard, in this manner pulling Vout low (to zero volts). Both T3 and T4 are OFF because of their door to-source voltages (Vgs) being at 0 volts, in this manner keeping any dc current. In the event that either An or B (or both) are low (at 0 volts), either T1 or T2 (or both) are OFF; T3 or T4 (or both) are ON hard, along these lines pulling Vout high to Vdd (a "1" yield). T4 Vout A T1 B T2 R. W. Knepper SC571, page 1-6

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A Vout B Simple CMOS Circuits: 2-way NOR Vdd Circuit Topology: T1 and T2 are N-FET gadgets associated in parallel with their sources at Gnd and channels at Vout; T3 and T4 are P-FET gadgets associated in arrangement. Inputs An and B are associated with the entryways of T1 & T3 and T2 & T4, individually. Operation: If either An or B is high, T1 or potentially T2 are ON hard and either T3 or T4 (or both) are OFF, pulling Vout to gnd. No dc current streams. On the off chance that both An and B are low (at gnd), both T1 and T2 are OFF and both T3 and T4 are ON hard, in this way pulling Vout to Vdd (a "1" yield). T1, T2, and T3 work as regular source, however T4\'s source potential will drop beneath Vdd. T3 T4 Vout T1 T2 A B Vout = A + B = A B R. W. Knepper SC571, page 1-7

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Vdd Vout A B C A Vout B C Simple CMOS Circuits: 3-way NAND Circuit Topology: T1,T2,T3 are N-FET gadgets in arrangement; T4,T5,T6 are P-FET gadgets in parallel with sources to Vdd. T3, T4, T5, & T6 all work as grounded source mode; T1 & T2 will have their source possibilities above gnd over bits of the exchanging transient, or if T3 is OFF Circuit Operation: If all of T1, T2, & T3 are ON (A, B, & C all high), Vout is pulled low; T4, T5, & T6 are all OFF hence keeping any dc current stream. On the off chance that (at least one) of A, B, or C are low, then the relating P gadget T4, T5, as well as T6 is ON hard and Vout is pulled high; in the meantime at least one of T1, T2, or potentially T3 is OFF keeping any dc current stream. T4 T5 T6 T1 T2 T3 Vout = A B C = A + B + C R. W. Knepper SC571, page 1-8

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Vdd T7 T8 T5 T6 V out A T3 T1 C T2 B T4 D V out = (A B) + (C D) Simple CMOS Circuits: Compound Logic Circuit Schematic: T1–T4 shape a parallel mix of arrangement associated NFET\'s; T5-T8 are an arrangement blend of parallel-associated PFET\'s. T2, T4, T7 & T8 work as grounded-source gadgets; T1, T3, T5 & T6 all have their deplete\'s entwined as V out . Take note of that the P gadget blend is masterminded reciprocal to the N gadget mix! Operation: If either An and B or C and D are high, NFET gadgets T1 and T2 or T3 and T4 are ON and haul V out down to ground potential (0 volts). No dc current streams. On the off chance that either An and C, or An and D, or B and C, or B and D are low, PFET gadgets T5 and T7, or T5 and T8, or T6 and T7, or T6 and T8 will be ON and pull Vout high to Vdd. No dc current streams. A B V out C R. W. Knepper SC571, page 1-9 D

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Simple CMOS Logic Circuits: Construction Algorithm Design the N-FET rationale blend to pull the yield down to zero, i.e. for all the min-terms in truth table with "0"s in the yield segment. N gadgets are ON when reality table data sources comparing to their separate entryway cathodes are "1"s; alternately, any truth table information sources that are zero infer that the relating N gadgets for those information sources are OFF. Plan the P-FET rationale mix to draw yield high to VDD, i.e. to cover all min-terms in truth table with "1"s in the yield section. P gadgets are ON when reality table information sources comparing to their individual doors are "0"s; on the other hand, P gadgets are OFF if the voltages on their separate entryways are at the "1" level. Begin with N pull down rationale and P pull up rationale which are corresponding to each other. At that point, search for approaches to rearrange the rationale mixes by evacuating gadgets having repetitive ways. R. W. Knepper SC571, page 1-10

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Vdd T7 T5 A T6 T8 B Z T3 A T1 An A T4 T2 B Z = (A B) + (A B) = (A B) (A B) = (A + B) (A + B) = (A B) + (A B) Simple CMOS Logic Circuits: XOR Circuit Schematic: 4 NFET\'s (T1-T4) and 4 PFET\'s (T5-T8) are built as four parallel segments of two arrangement gadgets each. Every arrangement association executes a min-term in reality table – two for Z=1 and two for Z=0. Could execute either tree first and after that apply supplement methodology, or utilize DeMorgan\'s hypothesis to actualize every min-term of truth table specifically. Operation: Output is pulled high to VDD by either A=1 and B=0 (turning on T5 and T6), or by A=0 and B=1 (turning on T7 and T8). Executes the "1" min-terms Output is pulled low to ground by either A=1 and B=1 (turning on T1 and T2), or by A=0 and B=0 (turning on T3 and T4). Executes the "0" min-terms R. W. Knepper SC571, page 1-11

Slide 12

Simple CMOS Logic Circuits: Examples from 1.5.5 I

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