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# Prologue to Computerized Rationale Outline Reference section An of CO&A Dr. Farag.

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Category: General / Misc
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2. . Boolean AlgebraGatesCombinational CircuitsSimplifications of Boolean FunctionsMultiplexers, Decoders, PLA, ROM, AddersSequential CircuitsFlip-FlopsRegistersCounters. Diagram. 3. . Like customary polynomial math however it characterizes an arrangement of intelligent operations and variablesBasic operations: AND, OR, NOT (., , _)These operations are characterized by their truth tablesOther operations can be gotten from t
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﻿Prologue to Digital Logic Design Appendix An of CO&A Dr. Farag

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Outline Boolean Algebra Gates Combinational Circuits Simplifications of Boolean Functions Multiplexers, Decoders, PLA, ROM, Adders Sequential Circuits Flip-Flops Registers Counters

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Boolean Algebra Similar to conventional polynomial math however it characterizes an arrangement of sensible operations and factors Basic operations: AND, OR, NOT ( . , + , _ ) These operations are characterized by their truth tables Other operations can be gotten from the essential ones. Ex: NAND, NOR, XOR, XNOR

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Boolean Algebra (Cont) It characterizes an arrangement of proposes and another arrangement of personalities that can be gotten from these hypothesizes A NAND E = NOT(AE) = Ā OR Ē. Verification?

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Gates To execute any rationale work we require a practically total arrangement of doors. Ex (AND, OR, NOT), (AND, NOT), (OR, NOT) (NAND), (NOR) How to execute every essential capacity by NAND?? Look at its truth table. Same for NOR From assembling perspective, utilizing just a single sort of doors to actualize the circuit is exceptionally worthwhile. Why? General - > Simple - > simple to outline - > shabby Gates are the essential building squares of every advanced framework. They are executed utilizing hardware segments (transistors, diodes, resistors, and so on.) Different families are TTL, CMOS, ECL, and so on. Not our issue

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Combinational Logic Circuits It is an interconnected arrangement of doors whose yield at any circumstances depends entirely on the contribution right then and there of time. ( NOT on a past yield state ) These circuits have n inputs & m yields. They can be characterized as far as truth tables, circuits outlines, or Boolean conditions Implement the accompanying truth by utilizing SOP or POS. Check equivalency

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Combinational Logic Circuits (rearrangements) Simplification: logarithmic tenets, karnaugh maps, or Quine-McKluskey tables The yield of Table 3 can be communicated: F = A\'BC\' + A\'BC + ABC\' = B(A\'+C\') ?? Issue: logarithmic principles depend principally upon perception & encounter A more deliberate approach to disentangle advanced rationale expressions is the utilization of karnaugh maps

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Combinational Logic Circuits (Karnaugh) The guide is a variety of 2 n squares (n # of sources of info) How would you fill the guide from a truth table?? To utilize an expression, it ought to be in sanctioned frame General principles of utilizing the guide: Combine ones into gatherings of (1, 2, 4, 8, … ) squares Form the biggest gathering size Form the min number of gatherings Two gathering ought not meet unless this will empower a little gathering to be bigger in size Some information blends might not happen and in this circumstance we call the yields, "couldn\'t care less" conditions These "ds" can be utilized as either 1 or 0 Example: outlining an incrementer for a BCD number, see Table 4 and Figure 10 in the accompanying slide

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Combinational Logic Circuits (Karnaugh) Exercise: Design a 4-bit combinational circuit 2\'s complementer (The yield creates the 2\'s supplement of the info twofold number)

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Combinational Logic Circuits (QMA) Quine-Mckluskey Algorithm is an orderly technique to get the base type of a Boolean expression The points of interest of the calculation are portrayed in the freebee The calculation is best depicted by a case Minimize the accompanying capacity F(A, B, C, D) = Σ (1, 5, 6, 7, 11, 12, 13, 15) This can be communicates as F = A\'B\'C\'D + A\'BC\'D + A\'BCD\' + A\'BCD + AB\'CD + ABC\'D\' + ABC\'D + ABCD The insignificant expression is F = A\'C\'D + A\'BC + ABC\' + ACD Quiz: Try it utilizing the decimal approach

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Applications of Combinational Logic Circuits NAND and NOR usage Multiplexer : a circuit that has numerous sources of info and just a single yield. Whenever one of the info is chosen as yield in view of the esteem on the select line(s) Below is reality table for a 4-to-1 multiplexer Implementation?? Application ex: Inputs to PC

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Applications of Combinational Logic (Cont) A decoder has n input lines and 2 n yield lines. Just a single yield line is chosen in view of the information Example: Instruction Op code unraveling With an extra info line, a decoder can be utilized as a demultiplexer which interfaces its single contribution to one of its yields in light of the esteem on the address lines PLA (Programmable Logic Array) has the target of building up a universally useful chip that can be promptly adjusted to particular purposes It can be executed by making each conceivable association through a circuit. Undesired associations are expelled by blowing their breakers This kind is called field-PLA See next slide

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Applications of Combinational Logic (Cont)

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Applications of Combinational Logic (Cont) ROM is viewed as a combinational circuit in light of the fact that the yields are a capacity just of the present sources of info

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Applications of Combinational Logic (Cont) How to execute the capacity of ALU. The essential circuit is the double viper Sum = A\'B\'C + A\'BC\' + ABC + AB\'C\' Carry = AB + AC + BC Implementation??

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Applications of Combinational Logic (Cont) We can shape n-bit adders by falling n 1-bit adders The convey of a unit is encouraged to the following one (swell adders) The issue with swell adders is the expanding defer The arrangement is utilizing convey lookahead system C 0 = A 0 B 0 C 1 = A 1 B 1 + A 1 A 0 B 0 + B 1 A 0 C 2 , … .. and so on. Typically a full snake (32-bit say) is developed from various modules (8-bit) adders where the conveys are undulated between modules however every module utilizes convey lookahead to infer inside convey signals. Test: Design a 8-bit convey lookahead snake utilizing two 4-bit units (infer all inward and outside convey flags and draw the last chart)

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Sequential Logic Circuits whose new yield depends on the present contribution as well as on the previous history of that contribution (as it were on the present yield as well) Basic application: making memory units (Flip-Flops) A Flip-Flop is a bistable gadget that has two yields (one is the supplement of the other: Q and Q\') S-R hook : Implementation two NORs with criticism

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Sequential Logic Circuits (Cont) S-R trademark or move table

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Sequential Logic Circuits (Applications) Clocked S-R Flip-Flop: Using AND at the information D Flip-Flop: One information is refuted and utilized as the second information. Usage & trademark table J-K Flip-Flop: it contrasts in that all information blends are permitted. The last case (J=K=1) causes the yield to flip, a vital component Implementation and table Flip-Flips are utilized to execute registers. There are two sorts of registers A parallel enroll is an arrangement of 1-bit recollections that can be perused or composed at the same time. See the accompanying slide A move enlist actualizes the poos work. See the accompanying slide

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Sequential Logic Circuits (Applications)

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Sequential Logic Circuits (Applications) Counters are a standout amongst the most vital applications A counter is an enlist whose esteem is increased by 1 modulo its ability upon the gathering of the clock Counters come into two flavors: Ripple counters: straight forward however moderate Synchronous counters: Faster yet more included

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Sequential Logic Circuits (Applications) Synchronous counters outline illustration. To begin with determine the excitation table of the JK Flip-Flop Construct reality table then outline the contribution to every lock For every info, utilize combinational plan to actualize the required circuit

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