Description

Versatile Electronics (PC, PDA, Wireless) IC Cost (Packaging and Cooling) Reliability ... Power: Portable Applications. The business sector of compact applications is ...

Transcripts

Prologue TO LOW-POWER DESIGN

Why Low-Power Devices? Useful reasons (Reducing power necessities of high throughput versatile applications) Financial reasons (Reducing bundling costs and accomplishing memory reserve funds) Technological reasons (Excessive warmth keeps the acknowledgment of high thickness chips and restricts their functionalities)

Application Fields Portable Electronics (PC, PDA, Wireless) IC Cost (Packaging and Cooling) Reliability (Electromigration, Latch-up) Signal Integrity (Switching Noise, DC Voltage Drop) Thermal Design Ultra-low-control applications Space missions (scaled down satellites)

Different Constraints for Different Application Fields Portable gadgets: Battery life-time Telecom and military: Reliability (lessened force diminishes electromigration, consequently builds unwavering quality) High volume items: Unit cost (reduced power diminishes bundling cost)

Design Technology Trend

Driving Forces for Low-Power: Portable Applications The business sector of convenient applications is becoming quickly. Worldwide Market for Cellular Phones

Driving Forces for Low-Power: Deep-Submicron Technology ADVANTAGES Smaller geometries Higher clock frequencies DISADVANTAGES Higher force utilization Lower unwavering quality

Driving Forces for Low-Power: Battery Limitations Battery greatest force and limit increments 10%-15% every year Increasing hole regarding power request

What has worked up to now? Voltage and procedure scaling Design approachs Power-mindful configuration streams and apparatuses, exchange zone for lower power Architecture Design Power down systems Clock gating, dynamic force administration Dynamic voltage scaling in view of workload Power cognizant RT/rationale blend Better cell library outline and resizing techniques Cap. decrease, limit control, transistor format

Opportunities for Power Savings

Realistic Estimation Expectations

Peak power P(t) RMS power Average force Energy t Power Metrics Average force: Related to battery lifetime. Crest power: Related to unwavering quality and warm disappointment RMS power: Related to cycle-by-cycle power Energy=power time: Related to power-delay item.

Why CMOS? V DD Intrinsically low power expending (when the info is static, there is no force utilization) Reference innovation Ease of configuration. PMOS V in V out NMOS Basic CMOS setup V SS

A NMOS entryway Polysilicon or Metal Oxide Gate Source Drain p n

A one-sided NMOS door V GS >0 + p n

A one-sided NMOS door V GS >0 + p n

A parallel plate capacitance A one-sided NMOS door V GS =V Tn + p n When V GS V Tn , the n-channel is produced and the gadget can begin operation by applying a positive V DS

Standard (Non-Adiabatic) Capacitance Change

Energy Stored in C

Energy Supplied by the Battery

Heat = Energy Dissipated (Non-Adiabatic)

Quasi-Adiabatic Charging of C

Sources of Power Consumption in CMOS

Power Dissipation in CMOS Circuits P absolute = P exchanging + P hamper P spillage Due to charging and releasing capacitors (dynamic force utilization) Due to direct ways Due to spilling diodes and transistors %75 %20 %5

C DD C GND Inverter: A Basic CMOS Gate

Inverter Analysis

Inverter Analysis

Energy Consumed (relate d to Battery Power) Energy expended because of a complete cycle 0 1 0.

Dynamic Power Consumption (identified with Battery Power) Average force utilization by a hub cycling at every period T : (every period has a 0 1 or a 1 0 move) Average force devoured by a hub with incomplete action (just a portion of the periods has a move)

Dynamic Power Consumption (identified with Inverter) Average force utilization by a hub cycling at every period T : (every period has a 0 1 or a 1 0 move) Average force devoured by a hub with halfway action (just a part of the periods has a move)

C L = C eff Dynamic Power Consumption Define successful capacitance C eff : To minimize exchanging power Reduce V DD Reduce C eff

Factors Influencing C eff Circuit capacity Circuit innovation Input probabilities Circuit topology

Some Basic Definitions Signal likelihood of a sign g(t) is given by Signal action of a rationale signal g(t) is given by where n g (t) is the quantity of moves of g(t) in the time interim between –T/2 and T/2 .

Factors Influencing C eff : Circuit Function Assume that there are M commonly autonomous signs g 1 , g 2 ,...g M each having a sign likelihood P i and a sign action An i , for i n. For static CMOS, the sign likelihood at the yield of a door is resolved by likelihood of 1s (or 0s) in the rationale portrayal of the entryway P 1 P 1 P 1 P 2 1-(1-P )(1-P 2 ) P 1-P 1 P 2 P 2

Factors Influencing C eff : Circuit Function (Static CMOS) Transistors associated with the same information are turning on and off at the same time when the info changes C L of a static CMOS door is charged to V DD at whatever time a 0 1 move at the yield hub is required. C L of a static CMOS entryway is released to ground whenever a 1 0 move at the yield hub is required. NOR Gate

A Y B Factors Influencing C eff : Circuit Function (Static CMOS) Two-information NOR door Assume stand out info move per cycle is permitted Assume inputs are equiprobable: p A =p B =1/2. The likelihood for the yield to be 1 is p Y =(1-p A )(1-p B )=1/4 The likelihood for the yield to be 0 is p Y \'=1-p Y =3/4

Factors Influencing C eff : Circuit Function (Static CMOS) State move chart of the NOR door

A Y B Factors Influencing C eff : Circuit Function (Static CMOS) Two-information X OR entryway Assume one and only info move per cycle is permitted Assume inputs are equiprobable: p A =p B =1/2. The likelihood for the yield to be 1 is p Y =(1-p A ) p B + (1-p B ) p A =1/2 The likelihood for the yield to be 0 is p Y \'=1-p Y = 1/2

Factors Influencing C eff : Circuit Function (Static CMOS) State move graph of the NOR entryway

f Factors Influencing C eff : Circuit Function ( Dynamic CMOS) At every cycle, MD is precharged to V DD. C L is precharged to V DD at every clock cycle It is released to ground at whatever time a 1 0 move at the yield hub is required. MD

A Y B Factors Influencing C eff : Circuit Function ( Dynamic CMOS) Two-info NOR entryway Assume stand out information move per cycle is permitted Assume inputs are equiprobable: p A =p B =1/2. The likelihood for the yield to be released is p Y " = 3/4 The likelihood of C L to be re-charged at the following cycle is p Y " .

Factors Influencing C eff : Circuit Function (Dynamic versus Static ) dynamic CMOS static CMOS : C eff (dynamic CMOS) C eff (static CMOS) Power because of glitching is much littler in element CMOS than it is in static CMOS. In static CMOS, the move likelihood relies on upon both info probabilities and past state. In element CMOS, the move likelihood relies on upon exclusively include probabilities. In static CMOS, the entryway yield does not switch if the inputs don\'t change between ensuing cycles. In element CMOS, the door yield may switch regardless of the fact that the inputs don\'t change between resulting cycles.

A Y B Factors Influencing C eff : Input Probabilities (Static CMOS) Two-info NOR entryway Assume stand out information move per cycle is permitted Assume inputs are not equiprobable: p A , p B The likelihood for the yield to be 1 is p Y =(1-p A )(1-p B ) The likelihood for the yield to be 0 is p Y \'=1-p Y

Factors Influencing C eff : Input Probabilities (Static CMOS) The likelihood for the yield of a NOR door to have a 0 1 move:

Factors Influencing C eff : Input Probabilities (Static CMOS) Signal likelihood figuring: For every information flag and entryway yield in the circuit, dole out a novel variable Starting from at the inputs and continuing to the yields, compose the expression for the yield of every entryway as an element of its information expression Suppress all examples in an offered expression to acquire the right likelihood for that sign (Recall that a type of a twofold number is additionally a double number)

Factors Influencing C eff : Input Probabilities (Static CMOS) Signal action computation: Boolean Difference It implies the condition under which yield f is sharpened to information x i If the essential inputs to capacity f are not spatially corresponded, the sign action at f is

Factors Influencing C eff : Input Probabilities (Static CMOS) Signal action through fundamental doors P 1 , A 1 P 2 A 1 + P 1 A 2 P 1 , An A P 2 , A 2 P 1 , A (1-P 2 ) A 1 + (1-P 1 ) A 2 P 2 , A 2 Signal action is utilized to decide dynamic force due to glitches.

Factors Influencing C eff : Circuit Topology Circuit topology may have high effect on C eff Example: Chain and Tree usage of a four information NAND entryway Assume static CMOS Assume all inputs are equiprobable.

Factors Influencing C eff : Circuit Topology Globally chain usage has a lower exchanging movement in the static conduct of the circuit. Timing skew between signs may bring about perils bringing about additional force dissemination. Consider 1110 1011 in chain circuit with unit postponement of every entryway.

Factors Influencing C eff : Circuit Topology The chain circuit experiences dangers,