Rationale Synthesis Using Cadence Ambit .

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Logic Synthesis Using Cadence Ambit. Environment Setup. Enter the following to .cshrc or a c-shell command file. setenv LM_LICENSE_FILE full_path/license.dat setenv AMBIT_SLIB_PATH .:lib1path:lib2path set path = (full_path/ambit3.0/BuildGates/v3.0/bin $path)
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Rationale Synthesis Using Cadence Ambit 1

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Environment Setup Enter the accompanying to .cshrc or a c-shell charge record. setenv LM_LICENSE_FILE full_path/license.dat setenv AMBIT_SLIB_PATH .:lib1path:lib2path set way = (full_path/ambit3.0/BuildGates/v3.0/canister $path) Use the accompanying to setup the NPU environment: % source/send out/home/instruments/setup/ambit/setup.cmd The device can be begun utilizing the "ac_shell" order. "ac_shell" is like Synopsys "dc_shell" charge. "ac_shell" charges can be conjured utilizing either the "- f" alternative or "source summon: % ac_shell –f design.ac Or ac_shell> source design.ac 2

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Getting Help under "ac_shell" bolsters the order like the "dc_shell". The help messages are extremely concise and they don\'t contain any cases like the dc_shell. One great element is that a halfway order can be entered, and ac_shell can list every one of the orders coordinating the fractional words: ac_shell> set_ 3

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dc_shell charges interpretation Most dc_shell orders can be mapped into ac_shell orders. ac_shell does not acknowledge dc_shell summons, however ac_shell can list the relating dc_shell orders: ac_shell> help dc_shell_command 4

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Library Compilation Ambit can utilize Synopsys .lib organize straightforwardly utilizing the "libcompile" charge: % libcompile npu018.lib npu018.alf "libcompile" keeps running as a remain solitary executable not at all like the Synopsys "read_lib" and "write_lib" orders which are upheld as dc_shell orders. 5

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Setting Library Search Path Technology look way is set from outside the ac_shell environment at the Unix provoke: % setenv AMBIT_SLIB_PATH .:lib1path:lib2path If the pursuit way is not set, the innovation libraries must be perused in with full way. The above is comparable to the usefulness of " search_path " charge in Synopsys dc_shell. 6

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Reading innovation libraries The "read_alf" charge can be utilized to peruse in innovation records: read_alf npu018.alf read_alf memory1.alf Target innovation library can be set utilizing the accompanying: set_global target_technology {npu018} Multiple objective innovation libraries can be set utilizing the accompanying: set_global target_technology {npu018 memory1_lib mem2_lib} 7

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Synthesis Directives Like Synopsys, Cadence bolsters combination mandates. At the point when Verilog HDL develop can be integrated into more than one executions, a mandate can be utilized. Rhythm ambit underpins the accompanying two styles:/ambit combination <directive>/* ambit blend <directive> */The most ordinarily utilized amalgamation orders are: case (full, parallel or mux) engineering (swell or cla) FSM (enum, state_vector) 8

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Full Case Directive Full case implies that the case expression can just assess to the qualities indicated by the case names (expressions). Full case is indicated as: case (exp)/ambit amalgamation case = full 4\'b000: f = … When the case is "full", it infers two things: No hook will be created. No default articulation is fundamental. 9

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Parallel Case Directive A parallel case implies that all the case branches have similar need of coordinating the case expression. Parallel case is determined as: case (case_exp)/ambit amalgamation case = parallel 4\'b0000 : f = … When the parallel order is indicated, no need structure is fabricated. 10

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Case Mux Directive Synopsys does not have this case order. At the point when a case articulation has the mux order, A mux is utilized as a part of unraveling the branches. (I don\'t have any experience utilizing this choice.) 11

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Architecture Selection Directive The design determination orders are utilized as a part of math expressions. The linguistic structure:/ambit combination engineering = cla or swell Example:/ambit blend design = swell dole out s = a + b; 12

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FSM Directives There are two FSM mandates enum and state_vector. "enum" is utilized to relate the state factors with the state esteem parameters: parameter/ambit union enum state_info S0 = 2\'b00, S1 = 2\'b10; reg[1:0]/* ambit blend enum state_info */ps; reg[1:0]/* ambit union enum state_info */ns; "state_vector" is utilized to determine the state enlist encoding plan:/ambit amalgamation state_vector ps –encoding one_hot dependably @(posedge clk) start … 13

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Reading in Verilog Files Like in dc_shell, Verilog documents can be perused in separately or as a gathering of records: read_verilog design.v read_verilog [glob submodule*.v] It should be noticed that, ac_shell does not permit "#" delays in the Verilog source code. They should be evacuated (for a few forms, notices are created for different variants). 14

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Define Clock Waveform Ambit requires a perfect clock to be characterized first with a name, period and waveform: rising edge falling edge set_clock ideal_clk –period 10 –waveform { 0 5} Clocks in the outline can be characterized utilizing the set_clock_arrival_time charge: set_clock_arrival_time –rise 0 –fall 5 –clock ideal_clk clkport A clock can be characterized straightforwardly under dc_shell. Both devices utilize perfect check in timing investigation of course. 15

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Define Input Constraints The set_data_arrival_time is utilized to characterize the relationship of the present chip as for the past one: set_data_arrival_time 0.0 –clock ideal_clock [find –port –input *] Arrival time of 0.0 implies that there is NO deferral by the past chip. The "- clock" alternative is not required for a combinational outline. Both dc_shell and ac_shell have similar semantics (which means.) 16

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Define Output Constraints Ambit utilizes information obliged time to compel the yields: set_data_required_time 10 –clock –ideal_clock [find –port –output *] The required time alludes to the measure of time inside the chip. dc_shell utilizes "set_output_delay" to determine the measure of time for the following chip. The "set_output_delay" identical order under Ambit is "set_external_delay": set_external_delay 0.0 –clock ideal_clock [find –port –output *] 17

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Setting different Constraints move limitation can be set utilizing slew_time_limit: set_global slew_time_limit 1.2 (worldwide) set_slew_time_limit 1.4 {A B C} "set_load" is comparable to set_port_capacitance_limit: set_global capacitance_limit 6 set_port_capacitance_limit 5 {pA pB} Fanout utmost can be upheld utilizing the accompanying: set_global fanout_load_limit 12 set_fanout_load_limit 8 {outportA outportB} 18

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Report Area The report_area can be utilized to report the aggregate zone for the present plan: ac_shell> report_area 19

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Report Timing The charge name for Ambit is additionally "report_timing". The equal " report_timing –delay max " in dc_shell is " report_timing –late " for ac_shell. The comparable " report_timing –delay min " in dc_shell is " report_timing –early " for ac_shell. Dissimilar to dc_shell, ac_shell does not report timing way if plan limitations are not set. 20

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Writing yield records The combine plan can be composed in Verilog arrange: write_verilog –hier design.vs The planning report document can be re-coordinated to a report record utilizing the standard Unix ">" and ">>" administrators. The SDF record can be composed out utilizing the "write_sdf" charge: write_sdf design.sdf 21

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Generating SDF Constraint File Many Placement & Routing devices can import timing limitations from a combination device. The Constraint record is ordinarily spared in the SDF arrange. Ambit can create a SDF requirement document utilizing the accompanying: write_constraint file_name Ambit composes the client\'s objective planning imperative, not the genuine way deferrals of the blended outline. 22

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Sample Script The accompanying is a specimen script utilizing two target libraries: read_alf mem.alf read_alf nlc18.alf read_verilog bist_top.v set_global target_technology {mem nlc18} do_build_generic set_top_timing_module func set_clock clkgrp –period 5.0 –waveform {0 5} set_clock_arrival_time –clock clkgrp 0.0 {BCLK, MCLK} set_data_arrival_time 0.0 –clock clkgrp [find –input –no_clock *] set_external_delay 0.0 –clock clkgrp [find –output *] do_optimize report_timing –max_paths 100 –late report_timing –max_paths 100 –early report_area write_verilog –hier design.vs write_sdf design.sdf 23

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Exercise Take a current outline by adapting it from the accompanying area:/send out/home/instruments/npu/ee561/control.v Create a clock with T = 2ns Set both input_delay and output_delay to be zero Synthesize it for utilizing Synopsys report both territory and postpone Repeat the same for Ambit Compare the outcomes 24

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