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Section 14.

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Category: General / Misc
Description
2. A Generic Digital Processor. 3. Building Blocks for Digital Architectures. Number juggling and Unit. - . . Bit-cut datapath. (viper, multiplier, shifter, comparator, and so forth.). Memory. - RAM, ROM, Buffers, Shift registers. Control. - Finite state machine (PLA, arbitrary rationale.). - Counters. Interconnect. - Switches.
Transcripts
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﻿Section 14 Arithmetic Circuits (I): Adder Designs Rev. 1.0 05/12/2003 Rev. 2.0 06/05/2003 Rev. 2.1 06/12/2003

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A Generic Digital Processor

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Building Blocks for Digital Architectures Arithmetic and Unit Bit-cut datapath ( viper, multiplier, shifter, comparator, and so forth.) - Memory - RAM, ROM, Buffers, Shift registers Control - Finite state machine (PLA, irregular rationale.) - Counters Interconnect - Switches - Arbiters - Bus

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Intel Microprocessor Itanium has 6 whole number execution units like this

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Bit-Sliced Design

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Itanium Integer Datapath Fetzer, Orton, ISSCC\'02

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Full-Adder (FA) Generate (G) = AB Propagate (P) = A B Å Delete = A B

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Boolean Function of Binary Full-Adder CMOS Implementation

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Express Sum and Carry as a component of P, G, D Define 3 new factor which ONLY rely on upon A, B Generate (G) = AB Propagate (P) = A B Å Delete = A B S C D and P Can likewise determine expressions for and in light of o Note that we will be now and again utilizing a substitute definition for + Propagate (P) = A B

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A B A B A B A B 0 1 2 3 C i ,0 o ,0 o ,1 o ,2 o ,3 FA = ( C ) i ,1 S 0 1 2 3 Carry-Ripple Adder Critical Path Worst-case postponement is straight with the quantity of bits t snake = ( N-1 ) t convey + t total t d = O( N ) Propagation delay (or basic way) is the most pessimistic scenario delay over all conceivable info designs A= 0001, B=1111, trigger the most pessimistic scenario delay A: 0 ��  1, and B= 1111 repaired to set the most pessimistic scenario defer move.

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Complimentary Static CMOS Full Adder 28 Transistors Logic exertion of Ci is lessened to 2 (c.f., An and B signals) Ci is late landing signal ��  close to the yield flag Co should be transformed ��  Slow down the swell proliferate

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Inversion Property

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Minimize Critical Path by Reducing Inverting Stages Exploit Inversion Property Reduce One inverter delay in every Full-snake (FA) unit

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Subtractor

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A Better Structure: The Mirror Adder Exploring the "Self-Duality" of the Sum and Carry capacities

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Mirror Adder Design The NMOS and PMOS chains are totally symmetrical A greatest of two arrangement transistors can be seen in the convey era hardware ��  for good speed. At the point when laying out the cell, the most basic issue is the minimization of the capacitance at hub C o . The capacitance at hub C o is made out of four dispersion capacitances, two inside entryway capacitances, and six door capacitances in the associating snake cell . The transistors associated with C i are set nearest to the yield.

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Transmission-Gate 6T XOR Gate Truth Table A=0: Pass B Signal A=1: Inverting B Signal

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Transmission-Gate Full Adder (24T) Same postponement for Sum and Carry ��  Multiplier outline

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Manchester Carry-Chain Adder Static Circuits Dynamic Circuits

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Manchester Carry Chain

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Manchester Adder Circuits (Weste) Dynamic Static Mux-based 4-bit Section sum<n>

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Manchester Adder Circuits (Cont.) Dynamic stage When CLK is low, the yield hub is pre-charged by the p pull-up transistor. At the point when CLK goes high, the draw down transistor turns on. In the event that convey produce G=AB is genuine  the yield hub releases. On the off chance that convey spread P=A+B is genuine  a past convey might be coupled to the yield hub, restrictively releasing it. Static stage This obliges P to be produced as A B The Manchester snake organize enhances the convey lookahead usage.

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P G P G P G P G 0 1 0 1 2 3 C i,0 o,3 o,0 o,1 o,2 Also called Carry-Skip FA P G P G P G P G 0 1 0 1 2 3 BP=P P o 1 2 3 C i,0 o,0 o,1 o,2 r e FA x e C l o,3 p i t l u M Carry-Bypass Adder Design Idea: If ( ) else Kill or Generate then C = C O,3 I,0

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Manchester Adder Circuits (Cont.) Wired OR The control signals T1,T2 ,and T3 appeared in Fig6(b) are produced by: T1 = - (P0P1P2)P3 T2 = - P3 T3 = P0P1P2P3 Fig6. Manchester viper with convey sidestep: (a) straightforward (b) struggle free

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Manchester Adder Circuits (Cont.) The most pessimistic scenario proliferation time of a Manchester snake can be enhanced by bypassing the four phases if all convey spread signs are valid. Fig. 6(b) utilizes a "contention - free" sidestep circuit, which enhances the speed by utilizing a 3-input multiplexer that counteracts clashes at the wired OR hub in the viper. In Fig. 6(b), the inverter displayed on the Cin flag has been moved to the focal point of the convey bind to enhance speed.

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Carry-Bypass Adder (cont.) t viper = t setup + M tcarry + ( N/M - 1) t sidestep + ( M - 1) t convey + t entirety M bits shape a Section ��  (N/M) Bypass Stages

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Carry Ripple versus Carry Bypass Wordlength (N) > 4~8 is better for Bypass Adder

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Setup P,G "0" Carry Propagation "0" "1" "1" Carry Propagation C o,k-1 2-to-1 Multiplexer o,k+3 Carry Vector Sum Generation Carry-Select Adder

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Carry-Select Adder Fig7. Convey select adder:(a) essential engineering (b) 32-bit convey select viper case

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Linear Carry Select

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Square Root Carry Select N-bit snake with P stages: 1 st organize includes M bits, 2 nd has (M+1) bits ��

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The straight development of snake convey delay with the extent of the information word for n-bit viper perhaps enhanced by computation the conveys to every phase in parallel. Convey Lookahead Adders

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Carry-Lookahead Adders (cont\'d) Carry of the ith organize - Expanding: For four phases, the fitting term: C0= G0 + P0C I C1= G1 + P1G0 + P1P0C I C2= G2 + P2G1 + P2P1G0 + P2P1P0C I C3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C I Fig1. Non specific convey lookahead snake

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Static CMOS Circuits Expanding Lookahead conditions: All the way:

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Dynamic CMOS Circuits The most pessimistic scenario postpone way in this circuit has six n-transistor in arrangement.

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Carry-Lookahead Adders Size and fan-in of the entryways expected to actualize this convey lookahead plan can plainly escape hand Number of phases of lookahead is generally constrained to around 4. The circuit and format are very sporadic contrasted and swell snake plans.

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Summary Datapath plans are basics for fast DSP, Multimedia, Communication computerized VLSI outlines. Most adders, multipliers, division circuits are presently accessible in Synopsys Designware under various territory/speed imperative. For subtle elements, check "Progressed VLSI" notes, or "PC Arithmetic" course books

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