Simple to Advanced Converters.


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Presentation Outline. Presentation: Analog versus Digital?Examples of ADC ApplicationsTypes of A/D ConvertersA/D Subsystem utilized as a part of the microcontroller chipExamples of Analog to Digital Signal ConversionSuccessive Approximation ADC. Initially Presenter. Byron Johns. Simple Signals. Simple signs
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Slide 1

Simple to Digital Converters Byron Johns Danny Carpenter Stephanie Pohl Harry "Bo" Marr October 4, 2005

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Presentation Outline Introduction: Analog versus Advanced? Cases of ADC Applications Types of A/D Converters A/D Subsystem utilized as a part of the microcontroller chip Examples of Analog to Digital Signal Conversion Successive Approximation ADC

Slide 3

First Presenter Byron Johns

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Analog Signals Analog signs – specifically quantifiable amounts as far as some other amount Examples: Thermometer – mercury tallness ascends as temperature rises Car Speedometer – Needle moves more remote all right quicken Stereo – Volume increments as you turn the handle.

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Digital Signals Digital Signals – have just two states. For advanced PCs, we allude to twofold states, 0 and 1. "1" can be on, "0" can be off. Cases: Light switch can be either on or off Door to a room is either open or shut

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Examples of A/D Applications Microphones - take your voice differing weight waves noticeable all around and change over them into fluctuating electrical signs Strain Gages - decides the measure of strain (change in measurements) when an anxiety is connected Thermocouple – temperature measuring gadget changes over warm vitality to electric vitality Voltmeters Digital Multimeters

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Just what does an A/D converter DO? Changes over simple signs into parallel words

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Analog ��  Digital Conversion 2-Step Process: Quantizing - separating simple esteem is an arrangement of limited states Encoding - relegating an advanced word or number to every state and coordinating it to the information flag

Slide 9

Step 1: Quantizing Example: You have 0-10V signs. Isolate them into an arrangement of discrete states with 1.25V augmentations. (How could we get 1.25V? See next slide… )

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Quantizing The quantity of conceivable states that the converter can yield is: N=2 n where n is the quantity of bits in the AD converter Example: For a 3 bit A/D converter, N=2 3 =8. Simple quantization measure: Q=(V max - V min )/N = (10V – 0V)/8 = 1.25V

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Encoding Here we relegate the computerized esteem (twofold number) to every state for the PC to peruse.

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Accuracy of A/D Conversion There are two approaches to best enhance precision of A/D transformation: expanding the determination which enhances the exactness in measuring the abundancy of the simple flag. expanding the examining rate which builds the most extreme recurrence that can be measured.

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Resolution (number of discrete qualities the converter can create) = Analog Quantization estimate (Q) (Q) = Vrange/2^n, where Vrange is the scope of simple voltages which can be spoken to constrained by flag to-clamor proportion (ought to be around 6dB) In our past illustration: Q = 1.25V, this is a high determination. A lower determination would be on the off chance that we utilized a 2-bit converter, then the determination would be 10/2^2 = 2.50V.

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Sampling Rate Frequency at which ADC assesses simple flag. As we find in the second picture, assessing the flag all the more frequently more precisely delineates the ADC flag.

Slide 15

Aliasing Occurs when the information flag is changing much quicker than the example rate. For instance, a 2 kHz sine wave being examined at 1.5 kHz would be remade as a 500 Hz (the associated flag) sine wave. Nyquist Rule: Use a testing recurrence at any rate twice as high as the most extreme recurrence in the flag to abstain from associating.

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Overall Better Accuracy Increasing both the testing rate and the determination you can acquire better precision in your AD flags.

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A/D Converter Types By Danny Carpenter Converters Flash ADC Delta-Sigma ADC Dual Slope (coordinating) ADC Successive Approximation ADC

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Flash ADC Consists of a progression of comparators, every one contrasting the info motion with a remarkable reference voltage. The comparator yields interface with the contributions of a need encoder circuit, which creates a twofold yield

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Flash ADC Circuit

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How Flash Works As the simple info voltage surpasses the reference voltage at each comparator, the comparator yields will consecutively immerse to a high state. The need encoder creates a parallel number in view of the most astounding request dynamic information, disregarding all other dynamic data sources.

Slide 21

ADC Output

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Advantages Simplest as far as operational hypothesis Most proficient as far as speed, quick restricted just regarding comparator and door engendering postpones Disadvantages Lower determination Expensive For each extra yield bit, the quantity of comparators is multiplied i.e. for 8 bits, 256 comparators required Flash

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Sigma Delta ADC Over inspected input flag goes to the integrator Output of mix is contrasted with GND Iterates to create a serial piece stream Output is serial piece stream with # of 1\'s corresponding to V in

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Outputs of Delta Sigma

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Advantages High determination No exactness outer segments required Disadvantages Slow because of oversampling Sigma-Delta

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Dual Slope Converter V in The examined flag charges a capacitor for a settled measure of time By incorporating after some time, clamor coordinates out of the change Then the ADC releases the capacitor at a settled rate with the counter numbers the ADC\'s yield bits. A more drawn out release time brings about a higher number t FIX t meas t

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Advantages Input flag is found the middle value of Greater clamor invulnerability than other ADC sorts High exactness Disadvantages Slow High exactness outside parts required to accomplish precision Dual Slope Converter

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Successive Approximation ADC By Stephanie Pohl A Successive Approximation Register (SAR) is added to the circuit Instead of including up paired grouping, this enlist checks by attempting all estimations of bits beginning with the MSB and completing at the LSB. The enroll screens the comparators yield to check whether the parallel tally is more prominent or not exactly the simple flag input and changes the bits in like manner

Slide 29

Successive Approximation ADC Circuit

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Output

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Advantages Capable of fast and dependable Medium precision contrasted with other ADC sorts Good tradeoff amongst speed and cost Capable of yielding the double number in serial (one piece at once) arrange. Disservices Higher determination progressive estimation ADC\'s will be slower Speed restricted to ~5Msps Successive Approximation

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ADC Types Comparison

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Successive Approximation Example 10 bit determination or 0.0009765625V of Vref Vin= .6 volts Vref=1volts Find the advanced estimation of Vin

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Successive Approximation MSB (bit 9) Divided V ref by 2 Compare V ref/2 with V in If V in is more prominent than V ref/2 , turn MSB on (1) If V in is not as much as V ref/2 , turn MSB off (0) V in =0.6V and V=0.5 Since V in >V, MSB = 1 (on)

Slide 35

Successive Approximation Next Calculate MSB-1 (bit 8) Compare V in =0.6 V to V=V ref/2 + V ref/4= 0.5+0.25 =0.75V Since 0.6<0.75, MSB is killed Calculate MSB-2 (bit 7) Go back to the last voltage that made it be turned on (Bit 9) and add it to V ref/8, and contrast and V in Compare V in with (0.5+V ref/8)=0.625 Since 0.6<0.625, MSB is killed

Slide 36

Successive Approximation Calculate the condition of MSB-3 (bit 6) Go to the last piece that made it be turned on (For this situation MSB-1) and add it to V ref/16, and contrast it with V in Compare V into V= 0.5 + V ref/16= 0.5625 Since 0.6>0.5625, MSB-3=1 (turned on)

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Successive Approximation This procedure proceeds for all the rest of the bits.

Slide 38

The HC11 and ADC By Harry "Bo" Marr

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Pin: 7 6 5 4 3 2 1 0 Port E (simple information) ADR1 - result 1 Analog Multiplexer ADR2 - result 2 Result Register Interface A/D Converter ADR3 - result 3 ADR4 - result 4 ADC Flow Diagram in HC11 8 channel/bit input V RL = 0 volts V RH = 5 volts Digital contribution on PE

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Stuctural Diagram of ADC on HC11 PE0 AN0 PE1 AN1 PE2 AN2 PE3 AN3 PE4 AN4 PE5 AN5 PE6 AN6 PE7 AN7 ANALOG MUX 8-bits CAPACITIVE DAC WITH SAMPLE AND HOLD V RH SUCCESSIVE APPROXIMATION REGISTER AND CONTROL V RL INTERNAL DATA BUS MULT SCAN CCF CD CC CB CA ADCTL A/D CONTROL RESULT REGISTER INTERFACE ADR1 ADR2 ADR3 ADR4 P 64 M68HC11 Family Data Sheet

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E Clock cycles: ADC by Clock cycle Conversion Sequence Sample (12) Bit 7 (4) 6 (2) _ (2) 0 (2) End (2) ADPU = 1 Successive estimate 1 st , ADR1 2 nd , ADR2 3 rd , ADR3 4 th , ADR4 CCF 0 32 64 96

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HC11 => 8 bits => 2 8 = 256 HC11 acknowledges 0 – 5V territory Voltage Range = (V RH – V RL )/255 * State

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0 Bit: 7 6 5 4 3 2 1 0 ADCTL Register $1030 CCF |No Op| SCAN |MULT | CD | CC | CB | CA 0 Read 0 - CCF : (1) after change cycle, (0) when composed to. Check : Continuous (1) or Not (0) MULT : Multi-Channel (1) or Single Channel (0) 0 = Single Channel is perused 4 times CD:CC:CB:CA = 0000 – 0111 Chooses input channel Chooses Channel Group when MULT = 1 Pg 27 – 28 in Reference Manual

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1 0 1 0 Bit: 7 6 5 4 3 2 1 0 Options Register $1039 ADPU |CSEL | IRQE |DLY | CME | NoOp| CR1 | CR0 1 - ADPU : Power up (1) hold up 100ms, No change (0) CSEL : utilize interior framework clock (1), utilize E-clock (0) IRQE : Falling Edge interupt (1), low level intrude on (0) DLY : Delay empowered (1), Delay incapacitated (0) CME : Monitor Clock (1), Don " t screen clock (0) CR[1:0] = Divide E clock by 1, 4, 16, 64. pg 38 in instructional booklet

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0 1 0 Bit: 7 6 5 4 3 2 1 0 Analog to Digital Results Register: $1031 - $1034 ADR2 ($1032) 0 Register $1032 = $02 Options Register ($1039) = $80 ADCTL Register ($1030) = $00 Just read in flag between 19.2 – 39.0 mV on stick E1!

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CSEL OPTION ($1039) ADPU IREQ DLY CME 0 CR1 CR2 SCAN MULT CD CC CB CA ADCTL ($1030) CCF 0 OP

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