Simple to Digital Converters .


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Analog to Digital Converters. Slow (Ramp) Medium (Successive Approx) Fast (Flash) Oversampling ( S-D ). Key components: Comparitors Sample-and-Hold D/A converters. Basic A/D Structure. +. Sample And Hold. Comparitors(s). Digital Outputs. Analog Input. -. D/A(s).
Transcripts
Slide 1

Simple to Digital Converters Slow (Ramp) Medium (Successive Approx) Fast (Flash) Oversampling ( S-D ) Key segments: Comparitors Sample-and-Hold D/A converters

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Basic A/D Structure + Sample And Hold Comparitors(s) Digital Outputs Analog Input - D/A(s) Digital Control

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Comparitors quantizing unit of ADCs Nonideal viewpoints: • Input balance voltage (static trademark) • Propagation time delay -Bandwidth (linear) -Slew rate (nonlinear)

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Slow-Speed A/D Converters

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Successive Approximation

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Successive Approximation Successive Approximation Algorithm: 1.) Start with the MSB bit and work toward the LSB bit. 2.) Guess the MSB bit as 1. 3.) Apply the advanced word 10000.... to a DAC. 4.) Compare the DAC yield with the inspected simple information voltage. 5.) If the DAC yield is more noteworthy, keep the figure of 1. On the off chance that the DAC yield is less, change the figure to 0. 6.) Repeat for the following MSB . In the event that the quantity of bits is N , the ideal opportunity for transformation will be NT where T is the clock time frame.

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Successive Approximation

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5bit Successive Approximation ADC

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More Details on the DAC

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Pipeline Algorithmic ADC Each stage: x by 2, + or – by Vref

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Self-Calibrating ADC

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Parallel/Flash A/D Converter Number of comparator required is 2 N - 1 Typical testing frequencies can be as high as 400MHz for 6-bits in sub-micron CMOS innovation.

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Interpolating ADCs Must get the pick up inside ½ LSB exact.

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Folding ADCs

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Schematic of a 5bit Folding ADC

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Folding Circuits Folding and insertion ADCs offer the most determination at high speeds (≈8 bits at 200MHz)

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Need discourse for gliding entryway Flash ADCs If no counterbalance by any stretch of the imagination, then estimating of gadgets can be upgraded for speed. In this way little info transistors: most elevated speed, and least information capacitance… .if littlest top in a run of the mill 0.35um process, entryway input capacitance is roughly 1fF; hence a 6bit would have an info capacitance of ~100fF with parasitics represented, which is sufficiently little… . (would require ~1kOhm yield resistance for a S/H to settle in 1ns Do we require S/H hinder here? Require pictures here.

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Two-Step Flash ADC

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Simple 4-bit Flash Converter

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Pipelined Flash ADC

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Part of a Two-Step ADC

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PIPELINE ADC WITH DIGITAL ERROR CORRECTION The ADC of the main stage utilizes 16 measure up to capacitors rather than 4 paired weighted for more exactness

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12-BIT PIPELINE ADC

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