Simple VLSI Design .

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Analog VLSI Design. Technology Trends. 3 Crises in VLSI Design. Power Crises. VLSI - Ever Increasing Power. Trends in Power, VDD and Current. Power/Delay Trade-Off. Leaky Transistors. 3 Strategies for Low Power. Low Power Strategies. Interconnect . Interconnect Trends.
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Simple VLSI Design Technology Trends

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3 Crises in VLSI Design

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Power Crises

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VLSI - Ever Increasing Power

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Trends in Power, VDD and Current

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Power/Delay Trade-Off

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Leaky Transistors

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3 Strategies for Low Power

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Low Power Strategies

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Interconnect Trends

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Interconnect Trends

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Design Issues

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Coupled Noise

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Which Way Forward?

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Future Chips 2014 

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ANALOG VLSI DESIGN Principles, Techniques, Building Blocks

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Is Analog VLSI Design Dead? Actually no, not genuine! Add up to simple chip deals for 2002 $39 billion, 2004 ~ $48billion 10% expansion over earlier year, development anticipated for next 3 years Raw transducer yield in many frameworks is simple in nature Although little %age of aggregate chip zone is simple, still a requirement for good outline hone since simple part might be the restricting component on general framework execution Days of immaculate simple plan are over, larger part of frameworks are coordinated with expanded usefulness in advanced area Will endeavor to present some chain of importance - utilize building square approach concerning computerized Bottom Line: Ability to outline both simple and advanced circuits and comprehend communications between the 2 spaces adds measurement to your plan portfolio

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Analog Building Blocks Basic Blocks incorporate Current Sources Current Mirrors Single Stage Amplifiers Differential Amplifiers & Op Amps Comparators Voltage References Data Converters Switched Capacitor Circuits

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CMOS Technology MOS Market overwhelms overall chip deals (>75%) Total MOS deals 2003/2004 ~ $250 billion Illustrates quality of CMOS innovation - highlight sizes now < 0.1um True framework level joining on a chip i.e. converters, channels, dsp processors, microcontroller centers, memory all live on one kick the bucket >180 million transistors/chip Decreases in highlight estimate cause a few complexities: Layout issues more vital Modeling is a key issue Parasitic impacts huge Power scattering issues testing (BiCMOS, VDD-jumping, and so on)

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Low Power + High Speed=BiCMOS Future of Gigascale Integration lies in BiCMOS innovation Application Example : Wireless Communications - pagers, mobile phones, portable PCs, palmtops Requirement for fast low power front end challenge for simple architects (can\'t manage the cost of time and vitality to digitize first) Historical Roadmap: Bipolar/CMOS 1930\'s – MOS concocted, didn\'t get on, lethargic for 30 yrs 1940\'s-50\'s – Bipolars imagined, got to be overwhelming through the mid 70\'s 1970\'s - Power utilization issues re-lighted enthusiasm for MOS 1980 MOS/Bipolar share of market 50/50 (to a great extent because of CMOS) 1983 – BiCMOS created 1990\'s – CMOS predominant 2000\'s - BiCMOS incorporated into CMOS, Gigascale Integration

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Improvement Trends Functionality (e.g. non-unpredictability, keen power) Integration Level (e.g. segments per chip, Moore\'s Law) Compactness (e.g. parts/sq cm) Speed (e.g. chip check in MHZ) Power (e.g. portable workstation or cellphone battery life) Cost (e.g. taken a toll for each capacity, verifiably diminishing) Available from scaling & tech changes over last 30yrs

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Future Trends: International Technology Roadmap for Semiconductors (ITRS) S/C industry has turned into a worldwide industry in the 90\'s: producers, providers, unions, overall operations. Since 1992 Semiconductor Industries Association (SIA) has created a 15year point of view toward significant patterns in the s/c industry (ITRS) Technical difficulties recognized Solutions proposed (where conceivable) Traditional is achieving major cutoff points New materials must be acquainted with further stretch out scaling limits Way to go: System In a Package (SiP P-SoC (Performance System-on-a-Chip): joining of numerous silicon advancements on a chip Nanotechnology Neuromorphic Systems - copy common flag handling (circuits working in subthreshold/frail reversal )

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ITRS: Technology Working Groups (TWG\'s) Purpose: To give direction, have and alter workshop in taking after zones Design Test Process Integration, Devices, Structures Front End Processes Lithography Interconnect Factory Integration Assembly & Packaging Cross Cutting Working Groups in environment, wellbeing, imperfection diminishment, metrology, displaying/reenactment

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ITRS: Example of Key Lithography-Related Characteristics Year 99 2002 2004 2008 DRAM pitch 180nm 130nm 110nm 70nm MPU Gate Length 140nm 100nm 70nm 45nm What is S-o-C (framework on a chip)? S-o-C chips are regularly blended innovation plans, including such assorted mixes as installed DRAM, superior or low-control rationale, simple, RF, elusive advances like Micro-Electro Mechanical Systems (MEMS) , optical info/yield. Time-to-market for specific application-particular ability is key Product families will be created around particular SoC structures and numerous SoC plans tweaked for target showcases by programming part (utilizing programming, FPGA, Flash, and others). Class of SoC is alluded to as a programmable stage . The outline apparatuses and advancements expected to amass, check, and program such installed SoC\'s will exhibit a noteworthy test throughout the following decade.

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Interconnect Working Group Function of interconnect is to appropriate clock and different flags and to give control/ground Requirement for interconnect is to meet the fast transmission needs of chips in spite of further scaling of highlight sizes. As supply voltage lessened, cross-talk an issue, close term arrangement is utilization of more slender copper metallization to lower line-to-line capacitance. In spite of the fact that copper-containing chips presented in 1998, copper must be consolidated with new encasing materials. Presentation of new low k dielectrics, CVD metal/hindrance/seed layers, and extra components for SoC, give handle combination challenges. Rising framework in-a-bundle (SiP) and framework on-a-chip, or SoC For long haul, material advancement with conventional scaling will no longer fulfill execution necessities. New plan or innovation arrangements, (for example, coplanar waveguides, free space RF, optical interconnect) will be expected to defeat the execution constraints of conventional interconnect.

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Analog VLSI Design ECE567 Spr 2008 Professor: Dr. Abby Ilumoka, Room UT 235, Ph: (860) - 768 - 5231 Email: ILUMOKANW@MAIL.HARTFORD.EDU Class Time: Mon 5.45pm – 8.15pm Office Hrs: Tues Thur 10.50am – 12.10pm, Mon 4-5pm, Wed 11-11.30am Credits: 3 credits Objectives: Course manages plan standards and systems for superior simple IC\'s executed in CMOS innovation. Albeit simple plan has all the earmarks of being significantly less precise than advanced, course highlights great outline standards to improve prepare. Course Text & Materials: 1. Simple Integrated Circuit Design by Johns & Martin, Wiley 1997 2. CMOS Circuit outline design & Simulation by Baker, Li & Boyce, IEEE Press, 1998 3. Determined diary & meeting papers Grading Policy and Exam Dates: 4 Exams - 4 X 25% = 100 % Laboratory/Design Assignments (reward max 10%) TOTAL 100% Spr 2008 Exam Dates: Exam 1 Mon Feb 18 Exam 2 Mon Mar 24 Exam 3 Mon Apr 21 Exam 4 Mon May 12

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TOPICS 1. Propelled MOS Modeling - Short Channel Effects - Sub-limit Operation - Leakage Currents 2. Handling and Layout for CMOS Analog Circuits 3. Major Building Blocks of Analog IC\'s - MOS Current Mirrors - Single Stage Amps - SPICE Simulation Examples 4. Outline of the 2 arrange CMOS Op Amp: Op Amp I 5. Plan of the 2 organize CMOS Op Amp: Op Amp II 6. Extra Analog Building Blocks - Comparators - Sample and Hold circuits - Switched capacitor Circuits 7. Information Converters A-D and D-A 8. Plan Refinement & Optimization Techniques 9.Noise Analysis and Modeling

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