Tending to and Guidelines (3).

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cse241L3 2. A straightforward cpu. All through the accompanying discourses, we pick as a modela straightforward CPU- - N universally useful registers (N=8,16)- - basic ALU- - basic direction set- - basic tending to repertoireNote: present day processors are extensively more complexthan the models given here. These models are illustrativeonly..
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Tending to and Instructions (3) A straightforward CPU Register-relative tending to A basic machine Addressing Modes Instruction Set Part 1: Data development + ALU Instruction Set Part 2: Flow of Control Simple Programs cse241L3 1

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A basic cpu Throughout the accompanying talks, we pick as a model a basic CPU - - N universally useful registers (N=8,16) - - basic ALU - - basic direction set - - basic tending to collection Note: present day processors are significantly more mind boggling than the models given here. These models are illustrative as it were. cse241L3 2

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A straightforward cpu (horribly misrepresented) PC R0 R1 IR Control Logic R7 ALU MAR MDR cse241L3 3

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General Purpose Registers General reason registers are CPU (Data Path) registers which - - give quick, typically transitory capacity of information - - are little in number (16,32,64) - - have no control work (think about PC, MAR, IR, MDR) - - are practically indistinguishable (i.e., there is normally no difference amongst Rj and Rk - however take note of that this is not generally genuine) - - we will assign these as R0,..,R7 ,...,R15 ,....,R31 cse241L3 4

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Operand Address Representation Consider a 32-bit machine. Assume we wish to speak to the direction clr a - signifying "clear the substance of memory area a" How might we speak to this guideline? assume we encode such guidelines in single word we have 32 bits for every word accordingly memory locations can be at most 32 bits wide however we need to encode the direction itself this will possess a few bits in the word cse241L3 5

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Sample Instruction Format 32 bits K bits 32-K bits Allocating K bits to encode the direction would give us a chance to have 2 K directions (more on this later) BUT The operand field has 32-K bits, NOT 32 bits Since the aggregate address space of this machine is 2 32 , there are a few locations which couldn\'t be spoken to in the 32-K bits which stay in the guideline (under direct tending to) cse241L3 6

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Sample Instruction Format (cont) 8 bits 24 bits maximum point of confinement of memory that can be tended to by 24 bits Suppose K = 8; then the operand field of the direction involves 24 bits; along these lines it can speak to the locations 0 to 2 24 - 1; yet it can\'t speak to the locations (numbers) 2 24 to 2 32 - 1 Memory cse241L3 7

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Indexing can take care of this issue; gave the file enroll is 32 bits in length, then all of memory can be gotten to by means of a file enlist. The utilization of a balance in the guideline essentially gives more noteworthy adaptability:- counterbalance + Index Register 32 bits The 32-bit list enlist can store all estimations of the deliver go 0 to 2 32 - 1; in this manner, all of memory can be tended to. Later we will see the circumstance appeared here being turned around. Memory cse241L3 8

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Register Addresses Like memory, registers can likewise have addresses These locations are utilized inside by the CPU to recognize registers Since there are less registers contrasted with the address space of the machine, far less bits are required to distinguish an enroll Suppose we have a machine with 8 General Purpose Registers (R0 - R7) - therefore, we require 3 bits to speak to the enlist addresses cse241L3 9

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Register-Relative Addressing We can utilize enlists as the essential vehicle for creating operand addresses This is a more "normal" tending to methodology than the methodologies already depicted Operands are put away in registers or memory Register locations are determined straightforwardly in guidelines Memory locations are generally indicated by means of the registers cse241L3 10

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Typical Register-Relative Addressing Modes NB: the phrasing utilized here can differ from writer to writer Register Direct the address in the direction is the address of the enlist which contains the operand Register Indirect the address in the direction is the address of the enlist whose substance are the address of the operand (in memory) Deferred the address in the guideline is the address of the enlist whose substance are the address of the memory area whose substance are the address of the memory area whose substance are the operand cse241L3 11

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Register Direct Value in operand field = 3 R3 - operand is the substance of R3 If we have N GPRs, we require ceil( log 2 N) bits to speak to the enlist address in a direction. (In this way 8 registers require 3 bits). An enroll operand is recognized in the direction by the esteem in a specific field of the guideline (see later). cse241L3 12

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Register Indirect Value in operand field = 3 R3 - substance of R3 is the address in memory of the operand 512 Operand is situated at memory area 512 cse241L3 13

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Register Deferred Value in operand field = 3 R3 - substance of R3 is the address in memory of the address of operand 512 Operand address is situated at memory area 512 1024 Operand is situated at 1024 cse241L3 14

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So, what do genuine tending to modes resemble? "Genuine tending to modes" rely on upon the machine. A few machines have complex tending to modes, some very trifling tending to modes The example underneath is from a more established (yet from multiple points of view prototypical) machine - the PDP-11 Refer to the content for PowerPC and Pentium See the sparc emulator later Refer to CSE240 for Pentium cse241L3 15

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Why the PDP-11 The PDP-11 is a collectible yet it had an assortment of tending to modes some of these modes are (generally) complex so it worth seeing these modes However you will see more present day tending to modes in the sparc later analyze another framework (Pentium) to the PDP11 cse241L3 16

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Addressing in the PDP-11 The PDP-11 executed 8 tending to modes (and had 8 enlists) The PDP-11 was a 16-bit machine (1 word = 2 bytes; see autoincrement and autodecrement beneath) Register-relative tending to is utilized (guidelines essentially contained enroll addresses, yet observe later) Consider how the PDP-11 actualized:- coordinate addressing backhanded tending to recorded tending to quick tending to cse241L3 17

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Addressing Modes in view of the PDP-11 cse241L3 18

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Contents of R4 focuses address of address of Operand is in area 380 Autoincrement Indirect (conceded) 128 R4 128 + 2 = 130 380 R4 is augmented (by 2 here) to direct now toward 130 cse241L3 19

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Instruction demonstrates an enlist to be utilized as file enlist + substance of enlist are added to 2\'s supplement counterbalance put away in the word taking after the direction; this is the address of the address of the Operand recovered from memory Indexed Indirect guideline cse241L3 20

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The part of the PC in enlist relative tending to The PC assumes a critical part in enlist relative tending to Consider the tending to modes 3 and 7 already (filed and ordered aberrant) Suppose we pick the PC as the list enlist What are the advantages of doing this? (See later) cse241L3 21

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Instruction Formats in light of the PDP-11 We have the accompanying: every word in the PDP-11 possesses 16 bits there are 8 enlists there are 8 tending to modes the PDP-11 has three sorts of guidelines (ordered by operand tally) 2 operand directions 1 operand directions 0 operand guidelines along these lines, we ought to have the capacity to conclude the direction arranges effectively cse241L3 22

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Representing Operands (in light of PDP-11) If we have 8 registers and 8 tending to modes, and if each tending to mode can apply to every enroll, then there are 64 add up to enlist/tending to mode blends, requiring 6 bits to speak to them:- 6 bit operand field 3 bits 3 bits to speak to speak to the tending to the enlist mode cse241L3 23

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2-and 1-operand guidelines 2-operand guidelines require a source and a goal operand; since every operand involves 6 bits (12 bits add up to), there are 4 bits accessible to store the OPCODE, the double esteem which recognizes the direction Opcode Source Operand Destination Operand 4 bits 6 bits (3+3) 6 bits (3+3) 1-operand directions require only a source operand; since this operand possesses 6 bits , there are 10 bits accessible to store the OPCODE, the parallel esteem which distinguishes the guideline. Opcode Operand 10 bits 6 bits (3+3) cse241L3 24

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0-operand directions and tallying guidelines A 0-operand direction has no operands; in this way every one of the 16 bits are accessible for use by the opcode. So we have the accompanying:- 2-operand directions 4 bit opcode field 1-operand guidelines 10 piece opcode field 0-operand instructions 16 bit opcode field Seems very clear:- there can be 16 2-operand guidelines 1024 1-operand directions 65536 0-operand directions But obviously this is not right. why not? cse241L3 25

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Counting Instructions The three guideline arrangements are demonstrated schematically above. Consider the twofold example 0110111010101110 Does it speak to a 2-operand direction, a 1-operand guideline or a 0-operand guideline? Consider the 2-operand guidelines. Review that 4 bits are utilized to indicate the opcode (the twofold representation of the guideline). Presently assume that each operand combine can be utilized by each 2-operand direction. There are 64 diverse conceivable source operands There are 64 distinctive conceivable goal operands Thus there are 64x64 = 4096 distinctive conceivable operand sets If there were 16 conceivable 2-operand directions, there would along these lines be ? distinctive opcode and operand match conceivable outcomes? There would be 16x4096 = 65536 such opcode/operand combine groupings c

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