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ADC Module. 12-bit determination ADC coreSixteen simple inputs (scope of 0 to 3V)Two simple info multiplexersUp to 8 simple data channels eachTwo test/hold units (for every information mux)Sequential and synchronous inspecting modesAuto sequencing capacity - up to 16 auto conversionsTwo free 8-state sequencers
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Module 6 : Analog Digital Converter C28x 32-Bit-Digital Signal Controller TMS320F2812 Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH)

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ADC Module 12-bit determination ADC center Sixteen simple information sources (scope of 0 to 3V) Two simple information multiplexers Up to 8 simple info stations every Two example/hold units (for every information mux) Sequential and synchronous examining modes Auto sequencing ability - up to 16 auto transformations Two free 8-state sequencers "Double sequencer mode" "Fell mode" Sixteen separately addressable outcome enrolls Multiple trigger hotspots for begin of-change External trigger, S/W, and Event Manager occasions

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ADC Module Block Diagram (Cascaded Mode) Analog MUX ADCINA0 Result MUX ADCINA1 MUX A S/H A ... RESULT0 RESULT1 ADCINA7 12-bit A/D Converter S/H MUX RESULT2 ADCINB0 . . . Result Select ADCINB1 MUX B S/H B EOC SOC ... RESULT15 Auto sequencer ADCINB7 MAX_CONV1 CHSEL00 (state 0) CHSEL01 (state 1) CHSEL02 (state 2) CHSEL03 (state 3) CHSEL15 (state 15) Software EVA EVB Ext Pin (ADCSOC) ... Begin Sequence Trigger

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ADC Module Block Diagram (Dual-Sequencer mode) Analog MUX Result MUX ADCINA0 RESULT0 ADCINA1 MUX A S/H A ... RESULT1 12-bit A/D Converter . . . ADCINA7 Result Select S/H MUX RESULT7 ADCINB0 Sequencer Arbiter ADCINB1 MUX B S/H B ... RESULT8 SOC1/EOC1 SOC2/EOC2 RESULT9 ADCINB7 . . . SEQ1 SEQ2 Result Select Auto sequencer Auto sequencer RESULT15 MAX_CONV1 MAX_CONV2 CHSEL00 (state 0) CHSEL01 (state 1) CHSEL02 (state 2) CHSEL07 (state 7) CHSEL08 (state 8) CHSEL09 (state 9) CHSEL10 (state 10) CHSEL15 (state 15) Software EVA Ext Pin (ADCSOC) ... ... Programming EVB Start Sequence Trigger Start Sequence Trigger

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F2812 ADC Clocking Example ADCCLKPS bits ADCTRL3 To CPU 1010b 000b CPS bit ADCTRL1 PLLCR DIV bits HISPCP 0011b 0b HSPCLK bits ADCTRL1 ACQ_PS bits 0111b CLKIN (30 MHz) SYSCLKOUT (150 MHz) HSPCLK (150 MHz) PCLKCR.ADCENCLK = 1 ADCCLK (25 MHz) FCLK (25 MHz) To ADC pipeline examining window FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK = FCLK/(CPS+1) testing window = (ACQ_PS + 1)*(1/ADCCLK) Important: ADCCLK can be a most extreme of 25 MHz!

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Analog-to-Digital Converter Registers Register Address Description ADCTRL1 0x007100 ADC Control Register 1 ADCTRL2 0x007101 ADC Control Register 2 ADCMAXCONV 0x007102 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x007104 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x007105 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x007106 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x007107 ADC Auto grouping Status Register ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x007109 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2 : ADCRESULT14 0x007116 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x007117 ADC Conversion Result Buffer Register 15 ADCTRL3 0x007118 ADC Control Register 3 ADCST 0x007119 ADC Status and Flag Register

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ADC Control Register 1 - Upper Byte ADCTRL1 @ 0x007100 ADC Module Reset 0 = no impact 1 = reset (set back to 0 by ADC rationale) Acquisition Time Prescale (S/H) Value = (binary+1) * Time subject to the "Transformation Clock Prescale" (Bit 7 "CPS") 15 14 13 12 11 10 9 8 held RESET ACQ_PS3 SUSMOD1 SUSMOD0 ACQ_PS2 ACQ_PS1 ACQ_PS0 Emulation Suspend Mode 00 = [Mode 0] free run (don\'t stop) 01 = [Mode 1] stop after current arrangement 10 = [Mode 2] stop after current transformation 11 = [Mode 3] stop promptly

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ADC Control Register 1 - Lower Byte ADCTRL1 @ 0x007100 Continuous Run 0 = stops in the wake of achieving end of succession 1 = nonstop (starts from the very beginning again from "introductory state") Sequencer Mode 0 = double mode 1 = fell mode 7 6 5 4 3 2 1 0 saved CPS saved SEQ1_OVRD SEQ_CASC CONT_RUN Sequencer Override (consistent run mode) 0 = sequencer pointer resets to "beginning state" at end of MAX_CONVn 1 = sequencer pointer resets to "beginning state" after "end state" Conversion Prescale 0 = CLK/1 1 = CLK/2

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ADC Control Register 2 - Upper Byte ADCTRL2 @ 0x007101 EVB SOC (fell mode just) 0 = no activity 1 = begin by EVB flag EVA SOC SEQ1 Mask Bit 0 = can\'t be begun by EVA trigger 1 = can be begun by EVA trigger Start Conversion (SEQ1) 0 = clear pending SOC trigger 1 = programming trigger-begin SEQ1 15 14 13 12 11 10 9 8 EVA_SOC_ SEQ1 INT_ENA_ SEQ1 EVB_SOC _SEQ INT_MOD _SEQ1 SOC_SEQ1 saved RST_SEQ1 saved Interrupt Enable (SEQ1) 0 = hinder impair 1 = hinder empower Reset SEQ1 0 = no activity 1 = quick reset SEQ1 to "starting state" Interrupt Mode (SEQ1) 0 = interfere with each EOS 1 = intrude on each different EOS

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ADC Control Register 2 - Lower Byte ADCTRL2 @ 0x007101 External SOC (SEQ1) 0 = no activity 1 = begin by flag from ADCSOC stick EVB SOC SEQ2 Mask bit 0 = can\'t be begun by EVB trigger 1 = can be begun by EVB trigger Start Conversion (SEQ2) (double sequencer mode just) 0 = clear pending SOC trigger 1 = programming trigger-begin SEQ2 7 6 5 4 3 2 1 0 EVB_SOC_ SEQ2 INT_ENA_ SEQ2 INT_MOD _SEQ2 EXT_SOC _SEQ1 saved RST_SEQ2 saved SOC_SEQ2 Interrupt Enable (SEQ2) 0 = hinder incapacitate 1 = hinder empower Reset SEQ2 0 = no activity 1 = prompt reset SEQ2 to "introductory state" Interrupt Mode (SEQ2) 0 = intrude on each EOS 1 = interfere with each different EOS

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ADC Control Register 3 ADCTRL3 @ 0x007118 ADC Reference Power Down 0 = shut down 1 = fueled up ADC Bandgap Power Down 0 = shut down 1 = controlled up ADC Power Down (aside from Bandgap & Ref.) 0 = shut down 1 = fueled up 15 - 8 7 6 5 saved ADCPWDN ADCBGND ADCRFDN 4 3 2 1 0 SMODE_SEL ADCCLKPS0 ADCCLKPS1 ADCCLKPS2 ADCCLKPS3 ADC Clock Prescale Sampling Mode Select 0 = consecutive testing mode 1 = synchronous examining mode

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Maximum Conversion Channels Register ADCMAXCONV @ 0x007102 MAX_ CONV 2_2 MAX_ CONV 2_1 MAX_ CONV 2_0 MAX_ CONV 1_3 MAX_ CONV 1_2 MAX_ CONV 1_1 MAX_ CONV 1_0 saved Bit fields characterize the most extreme number of auto transformations (binary+1) Cascaded Mode SEQ2 SEQ1 Dual Mode Auto change session dependably begins with the "underlying state" and proceeds successively until the "end state", if permitted SEQ1 SEQ2 Cascaded Initial state CONV00 CONV08 CONV00 End state CONV07 CONV15

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ADC Input Channel Select Sequencing Control Register Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 0x007103 CONV03 CONV02 CONV01 CONV00 ADCCHSELSEQ1 0x007104 CONV07 CONV06 CONV05 CONV04 ADCCHSELSEQ2 0x007105 CONV11 CONV10 CONV09 CONV08 ADCCHSELSEQ3 0x007106 CONV15 CONV14 CONV13 CONV12 ADCCHSELSEQ4

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Example - Sequencer "Begin/Stop" Operation EVA Timer 1 EVA PWM I 1 , I 2 , I 3 V 1 , V 2 , V 3 I 1 , I 2 , I 3 V 1 , V 2 , V 3 System Requirements: Three auto transformations (I 1 , I 2 , I 3 ) off trigger 1 (Timer sub-current) Three auto changes (V 1 , V 2 , V 3 ) off trigger 2 (Timer period) Event Manager An (EVA) and SEQ1 are utilized for this case with consecutive inspecting mode

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Example - Sequencer "Begin/Stop" Operation (Continued) RESULT0 I 1 RESULT3 V 1 RESULT1 I 2 RESULT4 V 2 RESULT2 I 3 RESULT5 V 3 MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to: Bits  15-12 11-8 7-4 3-0 0x007103 V 1 I 3 I 2 I 1 ADCCHSELSEQ1 0x007104 x V 3 V 2 ADCCHSELSEQ2 Once reset and instated, SEQ1 sits tight for a trigger First trigger three transformations performed: CONV00 (I 1 ), CONV01 (I 2 ), CONV02 (I 3 ) MAX_CONV1 esteem is reset to 2 (unless changed by programming) SEQ1 sits tight for second trigger Second trigger three transformations performed: CONV03 (V 1 ), CONV04 (V 2 ), CONV05 (V 3 ) End of second auto change session, ADC Results registers have the accompanying qualities:  User can reset SEQ1 by programming to state CONV00 and rehash same trigger 1, 2 session SEQ1 continues "holding up" at current state for another trigger

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ADC Conversion Result Buffer Register ADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117 (Total of 16 Registers) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB With simple information 0V to 3V, we have: simple volts converted value RESULTx 3.0 FFFh 1111|1111|1111|0000 1.5 7FFh 0111|1111|1111|0000 0.00073 1h 0000|0000|0001|0000 0 0h 0000|0000|0000|0000

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How would we Read the Result? Whole number organization x 0 x 0 x 0 x RESULTx bit move right 15 0 x ACC x Data Mem Example: read RESULT0 enroll #include "DSP281x_Device.h" void main(void) { Uint16 value; //unsigned esteem = AdcRegs.ADCRESULT0 >> 4; }

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Lab 6: Two Channel Analog Conversion started by GP Timer 1 AIM : AD-Conversion of ADCIN_A0 and ADCIN_B0 started by GPT1-time of 0.1 sec. ADCIN_A0 and ADCIN_B0 are associated with two potentiometers to control simple info voltages somewhere around 0 and 3,0V. no GPT1-intrude on administration  Auto-begin of ADC with T1TOADC-bit !! Utilize ADC-Interrupt Service Routine to peruse out the ADC comes about Use principle circle to indicate on the other hand the two outcomes as light-bar on LED\'s (GPIO port B7..B0)

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Additional Registers to introduce La

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