The Tablet PC at Five.


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Tablet prospects. Limits on PCs. What Moore really said. Suggestions for PCs. ... Managing idleness is the biggest issue for a PC framework planner. ...
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The Tablet PC at Five Chuck Thacker Distinguished Engineer Microsoft Corporation July 20, 2005

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Talk plot Tablet history The Tablet today Tablet prospects Limits on PCs What Moore really said. Suggestions for PCs. Different breaking points What about programming? Conclusions

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Prehistory – before 2000 Lots of prior endeavors – generally disappointments. DEC, Go, Newton, Pen Windows Technology wasn\'t prepared But vertical markets had restricted achievement. Required: better UI, better penmanship acknowledgment (without depending on it). Key: Better digitizer (with drift).

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A prior endeavor - 1983 TRS 80 Model 100 Reporters and understudies cherished it Ran for quite a long time on AA cells Solved most processing requirements for its (low goal) clients.

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Another endeavor - 1993 DEC Lectrice 5.5 pounds 1.5 hour battery Wireless system $5K LCD board VxWorks OS, X11 server advanced for perusing

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Where we began: Internal MS (1999) Microsoft confirmation of idea Transmeta TM5800 256MB DRAM, 20GB HDD 10.4" Slate Good focuses: Proved suitability Pushed the Power Efficiency Envelope 5 Hours runtime, 200 Hours standby Provided an improvement stage to get MS to Tablet PC dispatch. Then again: It was so sloooooow

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Tatung B12D 12.1" 1.2 GHz Centrino Today\'s Market: New Slates Motion Computing LE 1600 LS 800 Sahara i213 12.1", 1.6GHz Centrino NEC VersaPro, 10.4", 1.1 GHz Fujitsu 5000 10.4/12.1, Indoor/Outdoor 1.1 GHz ULV Tatung TTAB 10.4", 1 GHz ULV

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Acer C1xx Gateway M275 14.1", DVD 1.8 GHz Pentium-M C300 C250 SHARP Actius TN10W 12.1", 1.1 GHz Today\'s Market: New Convertibles Toshiba Averatec C3500 AMD 2200+ 12.1", DVD M200, 12.1" SXGA+ 2 GHz Pentium-M Electrovaya 1.4 GHz Centrino 12.1", Biometrics Scribbler SC-2200 Fujitsu T4000 HP tc4200 IBM ThinkPad x41 ViewSonic 12.1", 1 GHz

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Today\'s Market: New Hybrids & Ruggeds Ruggedized Hybrid Itronix 8.4", 933 MHz ULV HP Compaq TC1100ULV Celeron or Pentium 10.4", 1.1 GHz Walkabout Hammerhead 10.4", 4.5 lbs 933 MHz P-III M Xplore iX104 10.4" 1.1 GHz ULV

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Concept Design: New pivot

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A Concept Tablet for Kids Low power (7W) 8.4" presentation Tethered pen Rugged

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Other Form Factors Vulcan FlipStart OQO Model 1

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Today\'s Market: Forecasts 2004 Market offer 2006 Market offer 2008 Market offer Mobile Market Projections (IDC) Consumers, Mobile Professionals CY08 Market: 2.5M, CAGR (04-08): 40% 0% 1% 3% Ultra-Mobile 0 to 1 shaft, 5-8" screen, < 2 lbs. Versatile Professionals, Information Workers CY08 Market: 28.4M, CAGR (04-08): 51.4%, Ultra-Portable 1 or 2 spindle,10-12" screen, 2-4 lbs. 8% 17% 31% Information Workers, Consumers CY08 Market: 51M, CAGR (04-08): 22% Thin & Light 2 shaft, 14-15" screen, 4-7 lbs. 63% 56% Information Workers, Consumers CY08 Market: 8.9M, CAGR (04-08): - 11% 30% 19% 10% Transportable 2 & 3 shaft, 14-17" screen, 7-12 lbs. Information source: IDC

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Moore\'s Law (1967) Not generally a "law", yet a perception, expected to hold for "..the following couple of years". (Nt/A)(t1) = (Nt/A)(t0) * 1.58 t1-t0 (t in years) Most exponential bends in this present reality end up being "S" formed, however Moore\'s perception has held for a long time.

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The Wooly Bear Book of VLSI Scaling requires lithography and procedure changes. Get increasingly and quicker transistors in the same region. Power per transistor goes down, force per unit range goes up (in some cases far up). Power ≈ CV 2 f (in addition to spillage)

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How to utilize Moore\'s Law Lower cost: Same Nt, decreased A ("pass on psychologists") utilized as a part of video consoles. More intricate chips: Larger Nt, same A. Bring down the voltage and increment recurrence Add bigger reserves to conquer inertness Add design elements to increment ILP Superchips (SOC): Increase Nt and A.

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Moore\'s Law for Memory Capacity change: 1,000,000 X since 1970. Transfer speed change: 100 X. Dormancy lessening: just 10-20 X. Managing inactivity is the biggest issue for a PC framework creator.

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Moore\'s Law for Processors More intricate outlines More than one processor on a chip (homogeneous). More than one processor, with specific capacities, e.g. representation Graphics execution is enhancing much quicker than CPU execution.

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Thirty years of advancement

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Possible Future Limits Physical breaking points: "Molecules are too vast, and light is too moderate" Today, the issue isn\'t making the transistors speedier, it\'s the ideal opportunity for signs to proliferate on the wires (dormancy once more). Power. Heaps of transistors => loads of force. Cooling is hard. Plan multifaceted nature: Designing a billion-transistor chip takes an expansive group, even with great outline apparatuses. The "garbage DNA" issue. Financial aspects: Factories are exceptionally costly.

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Scaling Limits Voltage scaling is about over. It\'s difficult to work beneath 1 volt. Recurrence increments are additionally troublesome. Intel runs out at 3 – 4 GHz. Static spillage is likewise a major issue. Along these lines, we\'ll see more transistors later on, however they won\'t be better or quicker transistors.

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Future processors We\'ll see chips with numerous processor centers. Every center will be more straightforward than today\'s superscalar machines. Most likely hyperthreaded, to conceal inactivity. Improved to expand string level parallelism, instead of direction level parallelism. The tale about reserving is extremely indistinct… See Intel\'s "Stage 2015" white papers.

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Other Limits Not all advancements utilized as a part of PCs take after Moore\'s Law Disks don\'t Displays don\'t Batteries don\'t The data transfer capacity versus dormancy issue. See D. Patterson, "Idleness Lags Bandwidth", CACM, October 2004

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What about programming? For experimental registering and servers, the future appears to be fine. There are loads of vital issues that are embarrassingly parallel. For customer programming, the photo is more distressing.

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Many-center difficulties for customers Windows doesn\'t utilize strings well Exceptions: Kernel, SQL Competitors don\'t do any better Applications don\'t utilize strings well Outlook is the perfect case Until as of late, inking on Tablet was hazardous Problems: Writing multi-strung code is hard Threading model and primitives are excessively confused Threads don\'t create Debugging multi-strung code is harder Testing multi-strung code is a crapshoot Tool backing isn\'t great

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Possible ways forward Better dialect support for parallelism C ω , Atomic exchanges Better apparatuses Analyze liveness and security statically Model checking Dynamic race identification Better libraries Better instruction

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Conclusions Popularity of versatile gadgets, including Tablet PC, is developing Much of the advancement in the business is around there. Vitality proficiency can open up new markets. Silicon patterns support the top of the line There are loads of difficulties and open doors for new programming.

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