Transistor Definitions MOS - Metal Oxide Semiconductor FET - Field Effect Transistor BJT - Bipolar Junction TransistorSlide 3
deplete gatherer body base entryway source emitter npn bipolar transistor n-channel MOSFET and BJTSlide 4
Basic MOSFET ConstructionSlide 5
authority gatherer base emitter BJT Symbols pnp bipolar transistor npn bipolar transistorSlide 6
deplete door body entryway body source A circle is in some cases utilized on the door terminal to show dynamic low info source or deplete body entryway door source A. n - channel MOSFET B. p - channel MOSFET SymbolsSlide 7
Basic MOSFETSlide 8
Basic CMOS Logic Technology Based on the principal inverter circuit Transistors (two) are improvement mode MOSFETs N-channel with its source grounded P-channel with its source associated with +V Input: entryways associated together Output: channels associatedSlide 9
V DD p A Y = A\' n GND CMOS InverterSlide 10
CMOS Inverter - Operation Since the door is basically an open circuit it draws no present, and the yield voltage will be equivalent to either ground or to the power supply voltage, contingent upon which transistor is directing. At the point when input An is grounded (rationale 0), the N-channel MOSFET is fair-minded, and in this manner has no channel improved inside itself. It is an open circuit, and consequently leaves the yield line detached from ground. In the meantime, the P-channel MOSFET is forward one-sided, so it has a channel upgraded inside itself, interfacing the yield line to the +Vsupply. This pulls the yield up to +V (rationale 1). At the point when input An is at +V (rationale 1), the P-divert MOSFET is off and the N-channel MOSFET is on, in this manner pulling the yield down to ground (rationale 0). Consequently, this circuit effectively performs rationale reversal, and in the meantime gives dynamic draw up and pull-down, as per the yield state.Slide 11
+V Y = A + B A B CMOS 2-Input NORSlide 12
CMOS 2-Input NOR - Operation This essential CMOS inverter can be ventured into NOR and NAND structures by consolidating inverters in a mostly arrangement, halfway parallel structure. A functional case of a CMOS 2-input NOR entryway is appeared in the figure. In this circuit, if both information sources are low, both P-channel MOSFETs will be turned on, in this manner giving an association with +V. Both N-direct MOSFETs will be off, so there will be no ground association. Be that as it may, if either input goes high, that P-divert MOSFET will kill and separate the yield from +V, while that N-channel MOSFET will turn on, subsequently establishing the yield. Take note of the two p-divert FETs in arrangement.Slide 13
+V A B Y = A • B CMOS 2-Input NANDSlide 14
CMOS 2-Input NAND - Operation A two-input NAND door: a rationale 0 at either information will drive the yield to rationale 1; both contributions at rationale 1 will compel the yield to go to rationale 0. Take note of the two n-divert FETs in arrangement and the two p-direct FETs in parallel. The draw up and pull-down resistances at the yield are never the same, and can change fundamentally as the information sources change state, regardless of the possibility that the yield does not change rationale states . The outcome is uneven and capricious ascent and fall times for the yield flag. This issue was tended to, and was unraveled with the cushioned, or B-arrangement CMOS doors.Slide 15
+V Y = A • B CMOS 2-Input NAND: BufferedSlide 16
CMOS 2-Input NAND: Buffered The procedure here is to take after the genuine NAND entryway with a couple of inverters. Therefore, the yield will dependably be driven by a solitary transistor, either P-channel or N-channel. Since they are as firmly coordinated as could be expected under the circumstances, the yield resistance of the door will dependably be the same, and flag conduct is along these lines more unsurprising. Normally, the p-channel transistor is around twice as wide as the n-channel transistor, as a result of the distinction in conductivity amongst hardware and gaps. Take note of that we have not delved into the majority of the points of interest of CMOS door development here. For instance, to keep away from harm brought about by electricity produced via friction, diverse makers built up various info insurance circuits, to keep include voltages from turning out to be too high. Nonetheless, these insurance circuits don\'t influence the coherent conduct of the doors, so we won\'t delve into the points of interest here. This is not entirely valid for most CMOS gadgets for applications that are power-exchanged; uncommon data sources are required for power-off disengagement between circuits.Slide 17
Decoder Fundamentals Route information to one particular yield line. Choice of gadgets, assets Code transformations. Self-assertive exchanging capacities executes the AND plane Asserts one-of-many flag; at most one yield will be declared for any information mixSlide 19
Encoding Binary Decimal Unencoded Encoded 0 0001 00 1 0010 01 2 0100 10 3 1000 11 Note: Finite state machines might be unencoded ("one-hot") or double encoded. On the off chance that the all 0\'s state is utilized, then one less piece is required and it is called altered one-hot coding.Slide 20
Why Encode? A Logarithmic RelationshipSlide 21
A B 1 0 1 00 Y E Q 3 E Q 2 E Q 1 E Q 0 AND 2 A B AND 2 An A B AND 2 A D 0 A B AND 2 B D 1 2:4 Decoder What happens when the data sources goes from 01 to 10?Slide 22
A B C A B C A B C A B C 1 0 1 00 Y E Q 3 E Q 2 E Q 1 E Q 0 AND 3 AND 3 An AND 3 A D 0 D 1 ENABLE AND 3 B 2:4 Decoder with Enable 1 0 1 00Slide 23
Static HazardsSlide 24
A B A B A S B Y X1 Y X2 A B Y Static Hazard 2:1 Mux actualized by minimized Sum-of-Products Idealized coordinated postponementsSlide 25
A S B A B A B Y X1 Y X2 AND 2 A B Y OR 2 Y S D A BUFF AND 2 A Static Hazard In genuine circuits, delays don\'t precisely coordinate; Added delay for outlineSlide 26
We now have a "glitch." Static Hazard Same waveform, zoomed in.Slide 27
Static Hazard A B 1 0 1 0 1 0 S=0 S=1 1 0 1 0 Illustrating the minimized capacity on a Karnaugh outline. Just two 2-info AND doors are required for the item termsSlide 28
Static Hazard A B 1 0 1 0 1 0 S 1 0 1 0 The blue oval demonstrates the excess term used to cover the move between item terms.Slide 29
A S B A B A B A B Y X1 Y X2 Y X3 AND 2 A B C Y OR 3 Y S D A BUFF AND 2 An AND 2 Static Hazard How would we be able to confirm the nearness and operation of this entryway?Slide 30
0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 0000 16 A B C D D Q DFC1B CLR D Q DFC1B CLR D Q DFC1B CLR D Q DFC1B CLR Y TCNT AND 4 CLK CLDCK ACLR Static Hazard Terminal check of a 4-bit synchronous counter.Slide 31
D Q DF1 D Q DF1 D Q DF1 D Q DF1 CLK VCC Y S1 S0 D0 D1 D2 D3 Y A Y Y GND Static Hazard Flight Design Example TMR Triplet Majority Voter High-skew supportSlide 32
Static Hazard Flight Design Example Care is required when utilizing TMR circuits. To start with, the yield of the voter might be helpless to a rationale danger "glitch." This is not an issue if the TMR is encouraging the contribution of another synchronous info. Notwithstanding, the TMR yield ought to never encourage nonconcurrent sources of info, for example, flip-tumble timekeepers, clears, sets, read/compose inputs, and so on. "Outline Techniques for Radiation-Hardened FPGAs" Actel Corporation, September 1997 - in light of "SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space Applications and Device Characterization," R. Katz, R. Barto, et. al., IEEE Transactions on Nuclear Science, Dec. 1994.Slide 33
Static Hazard We have secured static dangers. There are additionally changing dangers. A case of a dynamic peril would be the point at which a circuit should switch as takes after: 0 1 But rather switches: 0 1 0 1 Any circuit that is static risk free is likewise rapid danger free.Slide 34
Common Output Stage Definitions V OH - Output voltage when driving high V OL - Output voltage when driving low I OH - Output current when driving high I OL - Output current when driving low T - Transition time, normally measured somewhere around 10% and 90% of the waveform (2.2 )Slide 35
V OH Test Configuration V CC Output Stage + Programmable Load i -Slide 36
V OL Test Configuration V CC Output Stage + V CC Programmable Load i -Slide 37
A1460A TID (V OH ) Test Post-IrradiationSlide 38
A1460A TID (V OL ) Test Post-IrradiationSlide 39
RT54SX32 TID (V OH ) Test Post-IrradiationSlide 40
RT54SX32 TID (V OL ) Test Post-IrradiationSlide 41
RT54SX16 Rise TimeSlide 42
RT54SX16 Fall TimeSlide 43
Common Interface Levels TTL 5V CMOS 5V PCI 3.3V PCI LVDS LVTTLSlide 44
TTL Voltage Specification V OH - 2.4 V OL - 0.5 V IH - 2.0 V IL - 0.8 V "1" Noise edge = 400 mV "0" Noise edge = 300 mVSlide 45
5V CMOS Voltages V OH - ~V DD (no DC stack) V OL - ~GND (No DC stack) V IH - 70% V DD V IL - 30% V DD "1" Noise edge = ~30% V DD "0" Noise edge =~30% V DD
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