Tutor Representation Reenactment Instruments for ASIC Outline.


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Coach Representation Recreation Apparatuses for ASIC Outline Victor P. Nelson ASIC Plan Stream Recreation Behavioral Model VHDL/Verilog Confirm Conduct Combination DFT/BIST and ATPG Entryway Level Netlist Check Work Full-custom IC Test vectors Transistor-Level Netlist Confirm Capacity
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Tutor Graphics Simulation Tools for ASIC Design Victor P. Nelson

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ASIC Design Flow Simulation Behavioral Model VHDL/Verilog Verify Behavior Synthesis DFT/BIST & ATPG Gate-Level Netlist Verify Function Full-custom IC Test vectors Transistor-Level Netlist Verify Function & Timing Standard Cell IC & FPGA/CPLD DRC & LVS Verification Physical Layout Map/Place/Route Verify Function & Timing IC Mask Data

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ADVance MS Digital, Analog, Mixed-Signal Simulation VHDL,Verilog, VHDL-AMS, Verilog-A, SPICE Netlists VITAL SPICE models Design_1 Design_2 IEEE 1164 Working Library Resource Libraries ADVance MS Input Stimuli Simulation Setup Mixed Signal (VHDL-AMS, Verilog-An) EZwave or Xelga Eldo, Eldo RF ModelSim Analog (SPICE) Mach TA Mach PA View Results Digital (VHDL,Verilog)

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Mentor Graphics Legacy Simulators Originally intended for PCB outline Quicksim II : computerized, door level reproduction Invoke : quicksim ASIC Design Kit : adk_quicksim Xilinx FPGA : pld_quicksim , Altera : max2_quicksim Quicksim Pro : blended schematic & HDL Uses both Quicksim II and Modelsim EE Invoke: qspro Accusim : simple recreation (SPICE) Invoke : adk_accusim

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Basic reenactment environment - Behavioral depiction, - Circuit structure/netlist, - Timing data, and so on. Conduct/ - Digital qualities, - Analog voltages/streams, - Waveforms - Generic, - Technology-particular Results postings, graphical waveforms, Reports of estimations, result checks, imperative infringement, and so forth

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Mentor Graphics ASIC Design Kit (ADK) ASIC innovation documents & standard cell libraries AMI: ami12, ami05 (1.2, 0.5 μ m) TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μ m) IC stream & DFT apparatus bolster records: Simulation VHDL/Verilog/Mixed-Signal models (Modelsim/ADVance MS) Analog (SPICE) models (Eldo/Accusim) Post-format confirmation (Mach TA) Digital schematic ( Quicksim II, Quicksim Pro) (exc. tsmc025,tsmc018) Synthesis library of sexually transmitted disease. cells (LeonardoSpectrum) Design for test & ATPG (DFT Advisor, Flextest/Fastscan) Schematic catch (Design Architect-IC) IC physical outline (standard cell & custom) Floorplan, place & course (IC Station) Design guideline check, design versus schematic, parameter extraction (Caliber)

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HDLs in Digital System Design Model and report computerized frameworks Hierarchical models System, RTL (Register Transfer Level), doors Different levels of reflection Behavior, structure Verify circuit/framework plan through reenactment Modelsim EE (VHDL, Verilog, System C) ADVance MS (above + VHDL-AMS, Verilog-A) Synthesize circuits from HDL models Leonardo (Synopsis)

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- count4.vhd 4-bit parallel-load synchronous counter LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY count4 IS PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); END count4; ARCHITECTURE rtl OF count4 IS SIGNAL int : unsigned(3 downto 0); BEGIN PROCESS(clear, clock, empower) BEGIN IF (clear = \'1\') THEN int <= "0000"; ELSIF (clock\'EVENT AND clock=\'1\') THEN IF (empower = \'1\') THEN IF (load_count = \'1\') THEN int <= D; ELSE int <= int + "01"; END IF; END IF; END IF; END PROCESS; Q <= int; END rtl; Typical VHDL behavioral model

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Test jolt: Modelsim “do” document: count4_rtl.do include wave/clock/clear/empower/load_count/D/Q include list/clock/clear/empower/load_count/D/Q power/clock 0, 1 10 - rehash 20 power/clear 0, 1 5, 0 10 power/empower 0, 1 25 power/load_count 0, 1 20, 0 35, 1 330, 0 350 power/D 10#5 0, 10#9 300 run 400

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Testbench: count4_bench.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; ENTITY count4_bench is end count4_bench; ARCHITECTURE test of count4_bench is part count4 PORT (clock,clear,enable,load_count : IN STD_LOGIC; D: IN unsigned(3 downto 0); Q: OUT unsigned(3 downto 0)); end segment; for all: count4 use substance work.count4(behavior); signal clk : STD_LOGIC := \'0\'; signal clr, en, ld: STD_LOGIC; sign clamor, qout: unsigned(3 downto 0); start C4: count4 port map(clk,clr,en,ld,din,qout); clk <= not clk after 10 ns; P1: procedure start commotion <= "0101"; clr <= \'1\'; en <= \'1\'; ld <= \'1\'; sit tight for 10 ns; clr <= \'0\'; sit tight for 20 ns; ld <= \'0\'; sit tight for 200 ns; end procedure; end; Alternative to “do” record Could check results & “assert” mistake messages

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Count4 – Simulation waveform Clear Counting Parallel Load

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ADVance MS : blended sign reproduction A/D converter advanced simple VHDL-AMS

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VHDL-AMS models D/A converter Comparator

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ADVance MS: blended Verilog-SPICE Verilog top (test seat) SPICE subcircuit

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Leonardo amalgamation methodology Invoke leonardo Select & load an innovation library (ASIC or FPGA) ASIC > ADK > TSMC 0.35 micron Read information VHDL/Verilog file(s): count4.vhd Enter any imperatives (clock freq, delays, and so on.) Optimize for territory/delay/exertion level Write yield file(s) count4_0.vhd - VHDL netlist (for recreation) count4.v - Verilog netlist (for IC format) count4.sdf - Standard postponement configuration document (for timing) count4.edf - EDIF netlist (for Xilinx/Altera FPGA)

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Leonardo-combined netlist count4_0.vhd library IEEE; use IEEE.STD_LOGIC_1164.all; library adk; use adk.adk_components.all; - ADDED BY VPN element count4 is port ( check : IN std_logic ; clear : IN std_logic ; empower : IN std_logic ; load_count : IN std_logic ; D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ; end count4 ; building design netlist of count4 is signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189: std_logic ; start Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ; Q_0_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear); ix127 : mux21_ni port guide ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable ); ix9 : oai21 port guide ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 ); ix170 : nand02 port guide ( Y=>nx169, A0=>D(0), A1=>load_count); Q_1_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136, CLK=>clock, R=>clear); ix137 : mux21_ni port guide ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> empower); ix29 : ao22 port guide ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22); ix15 : or02 port guide ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR); ix23 : aoi21 port guide ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count); Q_2_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear); ix147 : mux21_ni port guide ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> empower); ix49 : oai21 port guide ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189); ix182 : aoi21 port guide ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR); ix184 : nand02 port guide ( Y=>nx183, A0=>nx185, A1=>nx187); ix186 : inv01 port guide ( Y=>nx185, A=>load_count); ix188 : nand03 port guide ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR); ix190 : nand02 port guide ( Y=>nx189, A0=>D(2), A1=>load_count); Q_3_EXMPLR_EXMPLR : dffr port guide ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear); ix157 : mux21_ni port guide ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> empower); ix63 : mux21_ni port guide ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count); ix55 : xnor2 port guide ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187); end netlist ;

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Post-combination reenactment ( Leonardo - produced netlist) Verify integrated netlist matches behavioral model Create recreation primitives library for sexually transmitted disease cells: >vlib adk >vcom $ADK/innovation/adk.vhd >vcom $ADK/innovation/adk_comp.vhd Insert library/bundle assertion into netlist library adk; use adk.adk_components.all; Simulate in Modelsim, utilizing “do file” or test seat from unique behavioral reenactment results ought to match models of all ADK sexually transmitted disease cells

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Preparation for Layout Convert Verilog netlist to Mentor Graphics “EDDM” schematic/netlist organization Invoke Design Architect-IC (adk_daic) On menu bar, select File > Import Verilog Netlist document: count4.v (the Verilog netlist) Output catalog: count4 (for the EDDM netlist) Mapping document $ADK/innovation/adk_map.vmp Open the schematic for review Click Schematic in DA-IC palette Select schematic in registry named above (see next slide) Click Update LVS in the schematic palette to make a netlist to be utilized later by “Calibre” Create plan perspectives for ICstation apparatuses adk_dve count4 –t tsmc035 (V.P’s: format, lvs, sdl, tsmc035) Can likewise draw entryway/transistor schematics straightforwardly in DA-IC utilizing segments from the ADK library

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“count4” schematic (from Leonardo-created netlist)

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Simulating the schematic model Quicksim II (legacy – “Falcon Framework”) EDDM netlist mode

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