Understanding the illustrations pipeline.

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Understanding the illustrations pipeline. Address 2. Address Plot. An authentic point of view on the illustrations pipeline Measurements of development. Where we are today Settled capacity versus programmable pipelines A more intensive take a gander at the altered capacity pipeline Walk through the arrangement of operations
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Understanding the illustrations pipeline Lecture 2 http://www.cis.upenn.edu/~suvenkat/700/

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Lecture Outline An authentic viewpoint on the design pipeline Dimensions of advancement. Where we are today Fixed-capacity versus programmable pipelines A more intensive take a gander at the altered capacity pipeline Walk through the succession of operations Reinterpret these as stream operations We can program the settled capacity pipeline ! A few illustrations What constitutes information and memory, and how get to influences system outline. http://www.cis.upenn.edu/~suvenkat/700/

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The pipeline\'s development Elements of the design pipeline: A scene depiction: vertices, triangles, hues, lighting Transformations that guide the scene to a camera perspective “Effects”: texturing, shadow mapping, lighting counts Rasterizing: changing over geometry into pixels Pixel handling: profundity tests, stencil tests, and other per-pixel operations. Parameters controlling configuration of the pipeline: Where is the limit in the middle of CPU and GPU ? What exchange system is utilized ? What assets are given at every stride ? What units can get to which GPU memory components ? http://www.cis.upenn.edu/~suvenkat/700/

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Rasterization and Interpolation Raster Operations Generation I: 3dfx Voodoo (1996) One of the first genuine 3D diversion cards Worked by supplementing standard 2D feature card. Did not do vertex changes: these were done in the CPU Did do composition mapping, z-buffering. http://accelenation.com/?ac.id.123.2 Vertex Transforms Primitive Assembly Frame Buffer CPU GPU PCI http://www.cis.upenn.edu/~suvenkat/700/

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Rasterization and Interpolation Raster Operations Generation II: GeForce/Radeon 7500 (1998) Main advancement : moving the change and lighting counts to the GPU Allowed multi-texturing: giving knock maps, light maps, and others.. Speedier AGP transport rather than PCI http://accelenation.com/?ac.id.123.5 Vertex Transforms Primitive Assembly Frame Buffer GPU AGP http://www.cis.upenn.edu/~suvenkat/700/

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Rasterization and Interpolation Raster Operations Generation III: GeForce3/Radeon 8500(2001) For the first run through, permitted constrained measure of programmability in the vertex pipeline Also permitted volume texturing and multi-testing (for antialiasing) http://accelenation.com/?ac.id.123.7 Vertex Transforms Primitive Assembly Frame Buffer GPU AGP Small vertex shaders http://www.cis.upenn.edu/~suvenkat/700/

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Rasterization and Interpolation Raster Operations Generation IV: Radeon 9700/GeForce FX (2002) This era is the original of completely programmable representation cards Different renditions have distinctive asset limits on piece/vertex programs http://accelenation.com/?ac.id.123.8 Vertex Transforms Primitive Assembly Frame Buffer AGP Programmable Vertex shader Programmable Fragment Processor http://www.cis.upenn.edu/~suvenkat/700/

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Generation IV.V: GeForce6/X800 (2004) Not precisely a quantum jump, but… Simultaneous rendering to various cradles True conditionals and circles Higher accuracy throughput in the pipeline (64 bits end-to-end, contrasted with 32 bits before.) PCIe transport More memory/project length/surface gets to http://www.cis.upenn.edu/~suvenkat/700/

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Rasterization and Interpolation Raster Operations Fixed-capacity pipeline 3D API Commands 3D API: OpenGL or Direct3D 3D Application Or Game CPU-GPU Boundary (AGP/PCIe) GPU Command & Data Stream Vertex Index Stream Pixel Location Stream Assembled Primitives Pixel Updates GPU Front End Primitive Assembly Frame Buffer Transformed Vertices Transformed Fragments Pre-changed Vertices Pre-changed Fragments Programmable Fragment Processor Programmable Vertex Processor http://www.cis.upenn.edu/~suvenkat/700/

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A more intensive take a gander at the altered capacity pipeline http://www.cis.upenn.edu/~suvenkat/700/

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Pipeline Input Vertex Image F(x,y) = (r,g,b,a) (x, y, z) (r, g, b,a) (Nx,Ny,Nz) (tx, ty,[tz]) (tx, ty) (tx, ty) Material properties* http://www.cis.upenn.edu/~suvenkat/700/

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ModelView Transformation Vertices mapped from item space to world space M = model change (scene) V = view change (camera) Each grid change is connected to every vertex in the information stream. Think about this as a portion administrator. X Y Z 1 X’ Y’ Z’ W’ M * V * http://www.cis.upenn.edu/~suvenkat/700/

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Lighting Lighting data is joined with normals and different parameters at every vertex keeping in mind the end goal to make new hues. Color(v) = emissive + surrounding + diffuse + specular Each term in the right hand side is a vertex\'s element shading, position, typical and material properties. http://www.cis.upenn.edu/~suvenkat/700/

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Clipping/Projection/Viewport(3D) More lattice changes that work on a vertex to change it into the viewport space. Note that a vertex may be dispensed with from the info stream (on the off chance that it is cut). The viewport is two-dimensional: be that as it may, vertex z-quality is held for profundity testing. Clasp test is first illustration of a contingent in the pipeline. On the other hand, it is not a completely broad contingent. Why ? http://www.cis.upenn.edu/~suvenkat/700/

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Rasterizing+Interpolation All primitives are currently changed over to pieces. Information sort change ! Vertices to parts Fragment properties: (r,g,b,a) (x,y,z,w) (tx,ty), … Texture directions are interjected from surface directions of vertices. This gives us a straight addition administrator for nothing. Exceptionally USEFUL ! F(x, y) = (lo * x + range, lo’ * y + range’) http://www.cis.upenn.edu/~suvenkat/700/

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Per-part operations The rasterizer produces a surge of pieces. Every piece experiences a progression of tests with expanding unpredictability. Test 1: Scissor If (section lies in settled rectangle) let it breeze through else dispose of it Test 2: Alpha If ( fragment.a >= <constant> ) let it pass else toss it. Scissor test is comparable to cutting operation in section space rather than vertex space. Alpha test is extremely helpful for executing shadow maps. It is a marginally more broad restrictive. Why ? http://www.cis.upenn.edu/~suvenkat/700/

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Per-part operations Stencil test: S(x, y) is stencil cradle esteem for section with directions (x,y) If f(S(x,y)), let pixel pass else execute it. Upgrade S(x, y) restrictively relying upon f(S(x,y)) and g(D(x,y)). Profundity test: D(x, y) is profundity cradle esteem. On the off chance that g(D(x,y)) let pixel pass else execute it. Redesign D(x,y) restrictively. http://www.cis.upenn.edu/~suvenkat/700/

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Per-piece operations Stencil and profundity tests are more broad conditionals. Why ? These are the main tests that can change the condition of interior stockpiling (stencil cushion, profundity cradle). This is imperative . One of the overhaul operations for the stencil support is a “count” operation. Keep in mind this! Sadly, stencil and profundity cradles have lower exactness (8, 24 bits resp.) http://www.cis.upenn.edu/~suvenkat/700/

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Post-handling Blending: pixels are amassed into last framebuffer stockpiling new-val = old-val operation pixel-esteem If operation is +, we can whole all the (say) red segments of pixels that breeze through all tests. Issue: In generation<= IV, mixing must be done in 8-bit channels (the channels sent to the feature card); accuracy is restricted. We could utilize aggregation cradles, yet they are moderate. http://www.cis.upenn.edu/~suvenkat/700/

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Readback = Feedback What is the yield of a “computation” ? Show on screen. Render to support and recover values ( readback ) Readbacks are VERY moderate ! What alternatives do we have ? Render to off-screen cradles like gathering support Copy from framebuffer to composition memory ? Render specifically to a composition ? Stay tuned… PCI and AGP transports are unbalanced: DMA empowers quick exchange TO illustrations card. Converse exchange has customarily not been obliged, and is much slower. This inspires thought of “pass” being a nuclear “unit cost” operation. http://www.cis.upenn.edu/~suvenkat/700/

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Time for a puzzle… http://www.cis.upenn.edu/~suvenkat/700/

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An Example: Voronoi Diagrams. http://www.cis.upenn.edu/~suvenkat/700/

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Definition You are given n destinations (p 1 , p 2 , p 3 , … p n ) in the plane (think about every site as having a shading) For any point p in the plane, it is nearest to some site p j . Shading p with shading i. Register this hued guide on the plane. At the end of the day, Compute the closest neighbor outline of the locales. http://www.cis.upenn.edu/~suvenkat/700/

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Example http://www.cis.upenn.edu/~suvenkat/700/

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Hint: Think in one measurement higher The lower envelope of “cones” focused at the focuses is the Voronoi chart of this arrangement of focuses. http://www.cis.upenn.edu/~suvenkat/700/

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The Procedure keeping in mind the end goal to process the lower envelope, we have to focus, at every pixel, the part having the littlest profundity esteem. This should be possible with a straightforward profundity test. Permit a part to pass just on the off chance that it is littler than the present profundity support esteem, and redesign the cradle appropriately. The section that survives has the right shading. http://www.cis.upenn.edu/~suvenkat/700/

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Let’s make this more confused The 1-middle of an arrangement of destinations is a point q* that minimizes the total of separations from all locales to itself. q* = arg min Σ d(p, q) WRONG ! RIGHT ! http://www.cis.upenn.edu/~suvenkat/700/

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A First Step Can we register, for every pixel q, the quality F(q) = Σ d(p, q) We can utilize the cone trap from some time recently, and as opposed to figuring the base profundity worth, process the whole of all profundity qualities utilizing mixing. What’s the catch ? http://www.cis.upenn.edu/~suve

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