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Texas Instruments Joined European Client Preparing Center College of Connected Sciences Zwickau (FH)

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  1. Module 6 : Analogue Digital Converter C28x 32-Bit-Digital Signal Controller TMS320F2812 Texas Instruments Incorporated European Customer Training Center University of Applied Sciences Zwickau (FH)

  2. ADC Module • 12-bit resolution ADC core • Sixteen analog inputs (range of 0 to 3V) • Two analog input multiplexers • Up to 8 analog input channels each • Two sample/hold units (for each input mux) • Sequential and simultaneous sampling modes • Auto sequencing capability - up to 16 auto conversions • Two independent 8-state sequencers • “Dual-sequencer mode” • “Cascaded mode” • Sixteen individually addressable result registers • Multiple trigger sources for start-of-conversion • External trigger, S/W, and Event Manager events

  3. ADC Module Block Diagram (Cascaded Mode) Analog MUX ADCINA0 Result MUX ADCINA1 MUX A S/H A ... RESULT0 RESULT1 ADCINA7 12-bit A/D Converter S/H MUX RESULT2 ADCINB0 . . . Result Select ADCINB1 MUX B S/H B EOC SOC ... RESULT15 Auto sequencer ADCINB7 MAX_CONV1 CHSEL00 (state 0) CHSEL01 (state 1) CHSEL02 (state 2) CHSEL03 (state 3) CHSEL15 (state 15) Software EVA EVB Ext Pin (ADCSOC) ... Start Sequence Trigger

  4. ADC Module Block Diagram (Dual-Sequencer mode) Analog MUX Result MUX ADCINA0 RESULT0 ADCINA1 MUX A S/H A ... RESULT1 12-bit A/D Converter . . . ADCINA7 Result Select S/H MUX RESULT7 ADCINB0 Sequencer Arbiter ADCINB1 MUX B S/H B ... RESULT8 SOC1/ EOC1 SOC2/ EOC2 RESULT9 ADCINB7 . . . SEQ1 SEQ2 Result Select Auto sequencer Auto sequencer RESULT15 MAX_CONV1 MAX_CONV2 CHSEL00 (state 0) CHSEL01 (state 1) CHSEL02 (state 2) CHSEL07 (state 7) CHSEL08 (state 8) CHSEL09 (state 9) CHSEL10 (state 10) CHSEL15 (state 15) Software EVA Ext Pin (ADCSOC) ... ... Software EVB Start Sequence Trigger Start Sequence Trigger

  5. F2812 ADC Clocking Example ADCCLKPS bits ADCTRL3 To CPU 1010b 000b CPS bit ADCTRL1 PLLCR DIV bits HISPCP 0011b 0b HSPCLK bits ADCTRL1 ACQ_PS bits 0111b CLKIN (30 MHz) SYSCLKOUT (150 MHz) HSPCLK (150 MHz) PCLKCR.ADCENCLK = 1 ADCCLK (25 MHz) FCLK (25 MHz) To ADC pipeline sampling window FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK = FCLK/(CPS+1) sampling window = (ACQ_PS + 1)*(1/ADCCLK) Important: ADCCLK can be a maximum of 25 MHz!

  6. Analog-to-Digital Converter Registers Register Address Description ADCTRL1 0x007100 ADC Control Register 1 ADCTRL2 0x007101 ADC Control Register 2 ADCMAXCONV 0x007102 ADC Maximum Conversion Channels Register ADCCHSELSEQ1 0x007103 ADC Channel Select Sequencing Control Register 1 ADCCHSELSEQ2 0x007104 ADC Channel Select Sequencing Control Register 2 ADCCHSELSEQ3 0x007105 ADC Channel Select Sequencing Control Register 3 ADCCHSELSEQ4 0x007106 ADC Channel Select Sequencing Control Register 4 ADCASEQSR 0x007107 ADC Auto sequence Status Register ADCRESULT0 0x007108 ADC Conversion Result Buffer Register 0 ADCRESULT1 0x007109 ADC Conversion Result Buffer Register 1 ADCRESULT2 0x00710A ADC Conversion Result Buffer Register 2 ::::::::: ADCRESULT14 0x007116 ADC Conversion Result Buffer Register 14 ADCRESULT15 0x007117 ADC Conversion Result Buffer Register 15 ADCTRL3 0x007118 ADC Control Register 3 ADCST 0x007119 ADC Status and Flag Register

  7. ADC Control Register 1 - Upper ByteADCTRL1 @ 0x007100 ADC Module Reset 0 = no effect 1 = reset (set back to 0 by ADC logic) Acquisition Time Prescale (S/H) Value = (binary+1) * Time dependent on the “Conversion Clock Prescale” bit (Bit 7 “CPS”) 15 14 13 12 11 10 9 8 reserved RESET ACQ_PS3 SUSMOD1 SUSMOD0 ACQ_PS2 ACQ_PS1 ACQ_PS0 Emulation Suspend Mode 00 = [Mode 0] free run (do not stop) 01 = [Mode 1] stop after current sequence 10 = [Mode 2] stop after current conversion 11 = [Mode 3] stop immediately

  8. ADC Control Register 1 - Lower ByteADCTRL1 @ 0x007100 Continuous Run 0 = stops after reaching end of sequence 1 = continuous (starts all over again from “initial state”) Sequencer Mode 0 = dual mode 1 = cascaded mode 7 6 5 4 3 2 1 0 reserved reserved CPS reserved reserved SEQ1_OVRD SEQ_CASC CONT_RUN Sequencer Override (continuous run mode) 0 = sequencer pointer resets to “initial state” at end of MAX_CONVn 1 = sequencer pointer resets to “initial state” after “end state” Conversion Prescale 0 = CLK / 1 1 = CLK / 2

  9. ADC Control Register 2 - Upper ByteADCTRL2 @ 0x007101 EVB SOC (cascaded mode only) 0 = no action 1 = start by EVB signal EVA SOC SEQ1 Mask Bit 0 = cannot be started by EVA trigger 1 = can be started by EVA trigger Start Conversion (SEQ1) 0 = clear pending SOC trigger 1 = software trigger-start SEQ1 15 14 13 12 11 10 9 8 EVA_SOC_ SEQ1 INT_ENA_ SEQ1 EVB_SOC _SEQ INT_MOD _SEQ1 SOC_SEQ1 reserved RST_SEQ1 reserved Interrupt Enable (SEQ1) 0 = interrupt disable 1 = interrupt enable Reset SEQ1 0 = no action 1 = immediate reset SEQ1 to “initial state” Interrupt Mode (SEQ1) 0 = interrupt every EOS 1 = interrupt every other EOS

  10. ADC Control Register 2 - Lower ByteADCTRL2 @ 0x007101 External SOC (SEQ1) 0 = no action 1 = start by signal from ADCSOC pin EVB SOC SEQ2 Mask bit 0 = cannot be started by EVB trigger 1 = can be started by EVB trigger Start Conversion (SEQ2) (dual-sequencer mode only) 0 = clear pending SOC trigger 1 = software trigger-start SEQ2 7 6 5 4 3 2 1 0 EVB_SOC_ SEQ2 INT_ENA_ SEQ2 INT_MOD _SEQ2 EXT_SOC _SEQ1 reserved RST_SEQ2 reserved SOC_SEQ2 Interrupt Enable (SEQ2) 0 = interrupt disable 1 = interrupt enable Reset SEQ2 0 = no action 1 = immediate reset SEQ2 to “initial state” Interrupt Mode (SEQ2) 0 = interrupt every EOS 1 = interrupt every other EOS

  11. ADC Control Register 3ADCTRL3 @ 0x007118 ADC Reference Power Down 0 = powered down 1 = powered up ADC Bandgap Power Down 0 = powered down 1 = powered up ADC Power Down (except Bandgap & Ref.) 0 = powered down 1 = powered up 15 - 8 7 6 5 reserved ADCPWDN ADCBGND ADCRFDN 4 3 2 1 0 SMODE_SEL ADCCLKPS0 ADCCLKPS1 ADCCLKPS2 ADCCLKPS3 ADC Clock Prescale Sampling Mode Select 0 = sequential sampling mode 1 = simultaneous sampling mode

  12. Maximum Conversion Channels RegisterADCMAXCONV @ 0x007102 MAX_ CONV 2_2 MAX_ CONV 2_1 MAX_ CONV 2_0 MAX_ CONV 1_3 MAX_ CONV 1_2 MAX_ CONV 1_1 MAX_ CONV 1_0 reserved • Bit fields define the maximum number of auto conversions (binary+1) Cascaded Mode SEQ2 SEQ1 Dual Mode • Auto conversion session always starts with the “initial state” and continues sequentially until the “end state”, if allowed SEQ1 SEQ2 Cascaded Initial state CONV00 CONV08 CONV00 End state CONV07 CONV15 CONV15

  13. ADC Input Channel Select Sequencing Control Register Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0 0x007103CONV03 CONV02 CONV01 CONV00ADCCHSELSEQ1 0x007104CONV07 CONV06 CONV05 CONV04ADCCHSELSEQ2 0x007105CONV11 CONV10 CONV09 CONV08ADCCHSELSEQ3 0x007106CONV15 CONV14 CONV13 CONV12ADCCHSELSEQ4

  14. Example - Sequencer “Start/Stop” Operation EVA Timer 1 EVA PWM I1, I2, I3 V1, V2, V3 I1, I2, I3 V1, V2, V3 • System Requirements: • Three auto conversions (I1, I2, I3) off trigger 1 (Timer underflow) • Three auto conversions (V1, V2, V3) off trigger 2 (Timer period) • Event Manager A (EVA) and SEQ1 are used for this example • with sequential sampling mode

  15. Example - Sequencer “Start/Stop” Operation (Continued) RESULT0 I1 RESULT3 V1 RESULT1 I2 RESULT4 V2 RESULT2 I3 RESULT5 V3 • MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to: Bits  15-12 11-8 7-4 3-0 0x007103 V1 I3 I2 I1 ADCCHSELSEQ1 0x007104 x x V3 V2 ADCCHSELSEQ2 • Once reset and initialized, SEQ1 waits for a trigger • First trigger three conversions performed: CONV00 (I1), CONV01 (I2), CONV02 (I3) • MAX_CONV1 value is reset to 2 (unless changed by software) • SEQ1 waits for second trigger • Second trigger three conversions performed: CONV03 (V1), CONV04 (V2), CONV05 (V3) • End of second auto conversion session, ADC Results registers have the following values: •  User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session • SEQ1 keeps “waiting” at current state for another trigger

  16. ADC Conversion Result Buffer RegisterADCRESULT0 @ 0x007108 through ADCRESULT15 @ 0x007117(Total of 16 Registers) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSB LSB With analog input 0V to 3V, we have: analog volts converted value RESULTx 3.0 FFFh 1111|1111|1111|0000 1.5 7FFh 0111|1111|1111|0000 0.00073 1h 0000|0000|0001|0000 0 0h 0000|0000|0000|0000

  17. How do we Read the Result?Integer format x x x x x x x x x x 0 0 0 0 x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x 0 0 0 0 x x RESULTx bit shift right 15 0 x x ACC x x Data Mem Example: read RESULT0 register #include "DSP281x_Device.h" void main(void) { Uint16 value; // unsigned value = AdcRegs.ADCRESULT0 >> 4; }

  18. Lab 6: Two Channel Analogue Conversion initiated by GP Timer 1 AIM : • AD-Conversion of ADCIN_A0 and ADCIN_B0 initiated by GPT1-period of 0.1 sec. • ADCIN_A0 and ADCIN_B0 are connected to two potentiometers to control analogue input voltages between 0 and 3,0V. • no GPT1-interrupt-service  Auto-start of ADC with T1TOADC-bit !! • Use ADC-Interrupt Service Routine to read out the ADC results • Use main loop to show alternately the two results as light-beam on LED’s (GPIO port B7..B0)

  19. Additional Registers to initialize Lab 6: • General Purpose Timer Control : : GPTCONA • Timer 1 Control : T1CON • Timer 1 Period : T1PR • Timer 1 Compare : T1CMPR • Timer 1 Counter : T1CNT • Interrupt Flag : IFR • Interrupt Enable ask : IER • ADC – Control 3 : ADCTRL3 • ADC – Control 2 : ADCTRL2 • ADC – Control 1 : ADCTRL1 • Channel Select Sequencer 1 : CHSELSEQ1 • Max. number of conversions : MAXCONV • ADC - Result 0 : ADCRESULT0 • ADC - Result 1 : ADCRESULT1

  20. Optional Lab6A • Modify Lab-Exercise 4 ( ‘Knight-Rider’) : • use the Analogue Input ADCIN0 to change • the frequency for the LED’s • to add the ADC-setup use Lab6 as a start • use a LED-frequency range between 50Hz and 1 Hz • use (1) a linear or (2) a logarithm scale • between Fmin and Fmax.