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## Address 9 Combinational Programmed Test-Design Era (ATPG) Fundamentals

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**Lecture 9Combinational Automatic Test-Pattern Generation**(ATPG) Basics • Algorithms and representations • Structural vs. functional test • Definitions • Search spaces • Completeness • Algebras • Types of Algorithms VLSI Test: Lecture 9**Origins of Stuck-Faults**• Eldred (1959) – First use of structural testing for the Honeywell Datamatic 1000 computer • Galey, Norby, Roth (1961) – First publication of stuck-at-0 and stuck-at-1 faults • Seshu & Freeman (1962) – Use of stuck-faults for parallel fault simulation • Poage (1963) – Theoretical analysis of stuck-at faults VLSI Test: Lecture 9**Functional vs. Structural ATPG**VLSI Test: Lecture 9**Carry Circuit**VLSI Test: Lecture 9**Functional vs. Structural(Continued)**• Functional ATPG – generate complete set of tests for circuit input-output combinations • 129 inputs, 65 outputs: • 2129 = 680,564,733,841,876,926,926,749, 214,863,536,422,912 patterns • Using 1 GHz ATE, would take 2.15 x 1022 years • Structural test: • No redundant adder hardware, 64 bit slices • Each with 27 faults (using fault equivalence) • At most 64 x 27 = 1728 faults (tests) • Takes 0.000001728 s on 1 GHz ATE • Designer gives small set of functional tests – augment with structural tests to boost coverage to 98+ % VLSI Test: Lecture 9**Definition of Automatic Test-Pattern Generator**• Operations on digital hardware: • Inject fault into circuit modeled in computer • Use various ways to activate and propagate fault effect through hardware to circuit output • Output flips from expected to faulty signal • Electron-beam (E-beam) test observes internal signals – “picture” of nodes charged to 0 and 1 in different colors • Too expensive • Scan design – add test hardware to all flip-flops to make them a giant shift register in test mode • Can shift state in, scan state out • Widely used – makes sequential test combinational • Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence VLSI Test: Lecture 9**Circuit and Binary Decision Tree**VLSI Test: Lecture 9**Binary Decision Diagram**• BDD – Follow path from source to sink node – product of literals along path gives Boolean value at sink • Rightmost path: A B C = 1 • Problem: Size varies greatly with variable order VLSI Test: Lecture 9**Algorithm Completeness**• Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test • Untestable fault – no test for it even after entire tree searched • Combinational circuits only – untestable faults are redundant, showing the presence of unnecessary hardware VLSI Test: Lecture 9**Algebras: Roth’s 5-Valued and Muth’s 9-Valued**Symbol D D 0 1 X G0 G1 F0 F1 Failing Machine 0 1 0 1 X X X 0 1 Good Machine 1 0 0 1 X 0 1 X X Meaning 1/0 0/1 0/0 1/1 X/X 0/X 1/X X/0 X/1 Roth’s Algebra Muth’s Additions VLSI Test: Lecture 9**Roth’s and Muth’s Higher-Order Algebras**• Represent two machines, which are simulated simultaneously by a computer program: • Good circuit machine (1st value) • Bad circuit machine (2nd value) • Better to represent both in the algebra: • Need only 1 pass of ATPG to solve both • Good machine values that preclude bad machine values become obvious sooner & vice versa • Needed for complete ATPG: • Combinational: Multi-path sensitization, Roth Algebra • Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault VLSI Test: Lecture 9**Exhaustive Algorithm**• For n-input circuit, generate all 2n input patterns • Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs • Perform exhaustive ATPG for each cone • Misses faults that require specific activation patterns for multiple cones to be tested VLSI Test: Lecture 9**Random-Pattern Generation**• Flow chart for method • Use to get tests for 60-80% of faults, then switch to D-algorithm or other ATPG for rest VLSI Test: Lecture 9**Boolean Difference Symbolic Method (Sellers et al.)**g = G (X1, X2, …, Xn) for the fault site fj = Fj (g, X1, X2, …, Xn) 1 jm Xi = 0 or 1 for 1 in VLSI Test: Lecture 9**Boolean Difference (Sellers, Hsiao, Bearnson)**• Shannon’s Expansion Theorem: F (X1, X2, …, Xn) = X2F (X1, 1, …, Xn) + X2F (X1, 0, …, Xn) • Boolean Difference (partial derivative): Fj g • Fault Detection Requirements: G (X1, X2, …, Xn) = 1 Fj g = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = Fj (1, X1, X2, …, Xn) Fj (0, X1, …, Xn) = 1 VLSI Test: Lecture 9**Path Sensitization Method Circuit Example**• Fault Sensitization • Fault Propagation • Line Justification VLSI Test: Lecture 9**Path Sensitization Method Circuit Example**• Try path f – h – k – L blocked at j, since there is no way to justify the 1 on i 1 D D D D 1 D 0 1 1 VLSI Test: Lecture 9**Path Sensitization Method Circuit Example**• Try simultaneous paths f – h – k – L and g – i – j – k – L blocked at k because D-frontier (chain of D or D) disappears 1 D D 1 1 D D D 1 VLSI Test: Lecture 9**Path Sensitization Method Circuit Example**• Final try: pathg – i – j – k – L – test found! 0 0 D D 1 D D D 1 1 VLSI Test: Lecture 9**Boolean Satisfiability**• 2SAT: xi xj + xj xk + xl xm … = 0 xp xy + xr xs + xt xu … = 0 • 3SAT: xi xj xk + xj xk xl + xl xm xn … = 0 xp xy + xr xs xt + xt xu xv … = 0 . . . . . . VLSI Test: Lecture 9**Satisfiability Example for AND Gate**• Sak bk ck = 0 (non-tautology) or P (ak + bk + ck) = 1 (satisfiability) • AND gate signal relationships: Cube: • If a = 0, then z = 0 a z • If b = 0, then z = 0 b z • If z = 1, then a = 1 AND b = 1 z ab • If a = 1 AND b = 1, then z = 1 a b z • Sum to get: a z + b z + a b z = 0 (third relationship is redundant with 1st two) VLSI Test: Lecture 9**Pseudo-Boolean and Boolean False Functions**• Pseudo-Boolean function: use ordinary + -- integer arithmetic operators • Complementation of x represented by 1 – x • Fpseudo—Bool = 2 z + a b – a z – b z – a b z = 0 • Energy function representation: let any variable be in the range (0, 1) in pseudo-Boolean function • Boolean false expression: fAND (a, b, z) = z (ab) = a z + b z + a b z VLSI Test: Lecture 9**AND Gate Implication Graph**• Really efficient • Each variable has 2 nodes, one for each literal • If … then clause represented by edge from if literal to then literal • Transform into transitive closure graph • When node true, all reachable states are true • ANDing operator used for 3SAT relations VLSI Test: Lecture 9**Computational Complexity**• Ibarra and Sahni analysis – NP-Complete (no polynomial expression found for compute time, presumed to be exponential) • Worst case: no_pi inputs, 2 no_pi input combinations no_ff flip-flops, 4 no_ff initial flip-flop states (good machine 0 or 1 bad machine 0 or 1) work to forward or reverse simulate n logic gates an • Complexity: O (n x 2 no_pi x 4 no_ff) VLSI Test: Lecture 9**History of Algorithm Speedups**Algorithm D-ALG PODEM FAN TOPS SOCRATES Waicukauski et al. EST TRAN Recursive learning Tafertshofer et al. Est. speedup over D-ALG (normalized to D-ALG time) 1 7 23 292 1574 ATPG System 2189 ATPG System 8765 ATPG System 3005 ATPG System 485 25057 Year 1966 1981 1983 1987 1988 1990 1991 1993 1995 1997 VLSI Test: Lecture 9**Analog Fault Modeling Impractical for Logic ATPG**• Huge # of different possible analog faults in digital circuit • Exponential complexity of ATPG algorithm – a 20 flip-flop circuit can take days of computing • Cannot afford to go to a lower-level model • Most test-pattern generators for digital circuits cannot even model at the transistor switch level (see textbook for 5 examples of switch-level ATPG) VLSI Test: Lecture 9