Analog to Digital Converters • Slow (Ramp) • Medium (Successive Approx) • Fast (Flash) • Oversampling (S-D) Key components: Comparitors Sample-and-Hold D/A converters
Basic A/D Structure + Sample And Hold Comparitors(s) Digital Outputs Analog Input - D/A(s) Digital Control
Comparitors • quantizing unit of ADCs Nonideal aspects: • Input offset voltage (static characteristic) • Propagation time delay - Bandwidth (linear) - Slew rate (nonlinear)
Successive Approximation Successive Approximation Algorithm: 1.) Start with the MSB bit and work toward the LSB bit. 2.) Guess the MSB bit as 1. 3.) Apply the digital word 10000.... to a DAC. 4.) Compare the DAC output with the sampled analog input voltage. 5.) If the DAC output is greater, keep the guess of 1. If the DAC output is less, change the guess to 0. 6.) Repeat for the next MSB. If the number of bits is N, the time for conversion will be NT where T is the clock period.
Pipeline Algorithmic ADC Each stage: x by 2, + or – by Vref
Parallel / Flash A/D Converter Number of comparator required is 2N-1 Typical sampling frequencies can be as high as 400MHz for 6-bits in sub-micron CMOS technology.
Interpolating ADCs Must get the gain within ½ LSB accurate.
Folding Circuits Folding and interpolation ADCs offer the most resolution at high speeds (≈8 bits at 200MHz)
Need discussion for floating-gate Flash ADCs If no offset at all, then sizing of devices can be optimized for speed. Therefore small input transistors: highest speed, and lowest input capacitance….if smallest cap in a typical 0.35um process, gate input capacitance is approximately 1fF; therefore a 6bit would have an input capacitance of ~100fF with parasitics accounted for, which is small enough…. (would need ~1kOhm output resistance for a S/H to settle in 1ns Do we need S/H block here? Need pictures here.
PIPELINE ADC WITH DIGITAL ERROR CORRECTION The ADC of the first stage uses 16 equal capacitors instead of 4 binary weighted for more accuracy