Pipelining in William Stallings' Computer Organization and Architecture

This excerpt from the 7th edition explains how a CPU uses pipelining to speed up instruction execution by using registers such as the Program Counter, Instruction Register, Memory Address Register, and Memory Buffer Register.

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About Pipelining in William Stallings' Computer Organization and Architecture

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1. William Stallings Computer Organization and Architecture 7 th Edition 16

2. - / , , , pipelining -

3. / /-

4. CPU ( Program Counter PC ) ( Instruction Register IR) ( Memory Address Register MAR) ( Memory Buffer Register MBR) ( )

5. PC 1. PC MAR 2. . ( ) MBR 3. MBR IR O 4. PC

6. ( ) t1: MAR <- (PC) t1: MAR <- (PC) t2: MBR <- (memory) t2: MBR <- (memory) PC <- (PC) + t3: IR <- (MBR) t3: PC <- (PC) + : IR <- (MBR) PC MBR IR .

7. - - -

8. - - MAR <- (PC) MBR <- (memory) MBR <- (memory) & IR <- (MBR) PC <- (PC) + ALU -

9. MAR <- (IR address ) - IR MBR <- (memory) IR address <- (MBR address ) 2 - MBR 3 - IR

10.

11. t1: MBR <-(PC) t2: MAR <- save-address PC <- routine-address t3: memory <- (MBR) - . - -

12. (ADD) - .. ADD R1,X R1 R1 t1: MAR <- (IR address ) t2: MBR <- (memory) t3: R1 <- R1 + (MBR)

13. Execute Cycle (ISZ) ISZ X 1 0 t1: MAR <- (IR address ) t2: MBR <- (memory) t3: MBR <- (MBR) + 1 t4: memory <- (MBR) if (MBR) == 0 then PC <- (PC) + 1 if - t4

14. Execute Cycle (BSA) BSA X - Branch and save address BSA X X+1 t1: MAR <- (IR address ) MBR <- (PC) t2: PC <- (IR address ) memory <- (MBR) t3: PC <- (PC) + 1

15. - . . fetch, indirect, and interrupt cycles - opcode 2-bit Instruction cycle code (ICC) 00: Fetch 01: Indirect 10: Execute 11: Interrupt

16.

17. - - -

18. ALU

19. - CPU / CPU

20. - ( Sequencing ) CPU - / - :

21. ( Clock ) - - ( ) ( IR ) op-code ( Flags ) CPU Interrupts Acknowledgements

22. Model of Control Unit

23. CPU (.. R/W) I/O

24. - MAR <- (PC) PC MAR MBR <- (memory) MAR address bus data bus MBR

25.

26.